Apparatus and methods for control of sleep modes in a transceiver

Abstract

Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

What is claimed is: 
     
         1 . A wireless transceiver comprising:
 a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver; and   a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.   
     
     
         2 . The transceiver as defined in  claim 1 , wherein the sleep control logic is further configured to effect powering up of the at least a portion of the components independently and synchronously with a transceiver system timing. 
     
     
         3 . The transceiver as defined in  claim 1 , wherein the sleep control logic is further configured to shut down a partial number of components of the at least a portion of the components when a portion of signal processing of a received communication signal by the transceiver has been completed prior to a predetermined timing point and shut down another portion of components of the at least a portion of the components if signal processing by the processor is completed by predetermined time. 
     
     
         4 . The transceiver as defined in  claim 1 , wherein the sleep control logic is further configured to issue an interrupt signal to the processor configured to wake up the processor after determination of an end of a sleep mode by the sleep control logic. 
     
     
         5 . The transceiver as defined in  claim 1 , wherein the processor is configured to program the sleep control logic with the information sent to the sleep control logic. 
     
     
         6 . The transceiver as defined in  claim 1 , wherein the sleep control logic is part of baseband receiver configured to receive burst communication signals. 
     
     
         7 . The transceiver as defined in  claim 1 , wherein the sleep control logic is configured to determine an end timing of a sleep mode and initiate wakeup of at least a portion of components in the transceiver. 
     
     
         8 . The transceiver as defined in  claim 7 , wherein the sleep control logic is configured to issue a wakeup interrupt signal to the processor after determining an end timing of a sleep mode. 
     
     
         9 . The transceiver as defined in  claim 1 , wherein the wakeup interrupt signal is a dynamic parameter determined by the processor after each received burst of data. 
     
     
         10 . Computer-readable medium encoded with a set of instructions, the instructions comprising:
 an instruction for determining timing information concerning sleep periods for at least a portion of components within the transceiver with a processor;   an instruction for receiving information concerning sleep periods from the processor with a sleep control logic coupled to the processor; and   an instruction for shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with a transceiver system timing.   
     
     
         11 . The computer program product of  claim 10 , wherein the computer-readable medium further comprises:
 code for causing a processor to use the sleep control logic to shut down a partial number of components of the at least a portion of the components of the receiver when a portion of signal processing of a received communication signal by the transceiver has been completed prior to a predetermined timing point and shut down another portion of components of the at least a portion of the components of the receiver if signal processing by the processor is completed by a predetermined time.   
     
     
         12 . The computer program product of  claim 10 , wherein the computer-readable medium further comprises:
 code for causing a processor to determine an end of a sleep mode with the sleep control logic; and   code for causing a processor to issue an interrupt signal to the processor with the sleep control logic operable to wake up the processor based on the determination of the end of the sleep mode.   
     
     
         13 . The computer program product of  claim 10 , wherein the computer-readable medium further comprises:
 code for causing a processor to program the sleep control logic with the timeline.   
     
     
         14 . The computer program product of  claim 10 , wherein the computer-readable medium further comprises:
 code for causing a processor to receive burst communication signals.   
     
     
         15 . The computer program product of  claim 10 , wherein the computer-readable medium further comprises:
 code for causing a processor to determine an end timing of a sleep mode; and   code for causing a processor to initiate a wakeup of the at least a portion of the components of the receiver.   
     
     
         16 . The computer program product of  claim 15 , wherein the computer-readable medium further comprises:
 code for causing a processor to issue a wakeup interrupt signal to the processor after determining an end timing of a sleep mode.   
     
     
         17 . The computer program product of  claim 16 , wherein the wakeup interrupt signal is a dynamic parameter determined by the processor after a received burst of data.