Delay adjustment device, semiconductor device and delay adjustment method

Abstract

A semiconductor device including a terminal configured to receive data strobe signals from a memory in an adjustment mode, a strobe value retrieve unit coupled to the terminal to latch the data strobe signals at a plurality of different timings in the adjustment mode, and an adjustment circuit configured to determine in the adjustment mode when to make a data strobe signal valid in a normal operation mode, based on latch results at the plurality of the different timings.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a terminal configured to receive data strobe signals from a memory in an adjustment mode;   a strobe value retrieve unit coupled to the terminal to latch the data strobe signals at a plurality of different timings in the adjustment mode; and   an adjustment circuit configured to determine in the adjustment mode when to make a data strobe signal valid in a normal operation mode, based on latch results at the plurality of the different timings.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising an input buffer coupled between the terminal and the strobe value retrieve unit to receive the data strobe signals. 
     
     
         3 . The semiconductor device according to  claim 2 , further comprising a mask circuit configured to receive the data strobe signals and a valid signal which makes the data strobe signal valid. 
     
     
         4 . The semiconductor device according to  claim 3 , further comprising a delay unit coupled to the mask circuit. 
     
     
         5 . The semiconductor device according to  claim 4 , further comprising another terminal configured to receive data signal; and
 a flip-flop coupled to the another terminal and the delay circuit.   
     
     
         6 . The semiconductor device according to  claim 3 , further comprising a valid signal output circuit configured to output the valid signal. 
     
     
         7 . The semiconductor device according to  claim 5 , further comprising a variable delay circuit coupled to the flip-flop. 
     
     
         8 . The semiconductor device according to  claim 5 , further comprising another input buffer coupled between the another terminal and the flip-flop.