I-q mismatch calibration and method

Abstract

Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.

1 . An apparatus comprising:
 a unidirectional current digital to analog converter configured to convert an input current to an analog current;   a voltage digital to analog converter configured to convert a base digital voltage to a base analog voltage; and   a circuit comprising a plurality of sets of switches and two buffers, and wherein voltage output from a first buffer is based on the analog current and base analog voltage and is greater than voltage output from a second buffer by a voltage offset when a first set of switches is closed, and voltage output from the second buffer is based on the analog current and base analog voltage and is greater than voltage output of the first buffer by the voltage offset when a second set of switches is closed.   
     
     
         2 . The apparatus of  claim 1 , wherein the base analog voltage is provided to the first buffer when the second set of switches is closed and to the second buffer when the second set of switches is closed. 
     
     
         3 . The apparatus of  claim 1 , wherein voltage output from the first buffer and the second buffer is provided to a variable resistor controlled by a range control device. 
     
     
         4 . The apparatus of  claim 3 , wherein output from the variable resistor is combined with the analog current to form a feedback sum. 
     
     
         5 . The apparatus of  claim 4 , wherein the feedback sum is provided to the first buffer when the first set of switches is closed and to the second buffer when the second set of switches is closed. 
     
     
         6 . The apparatus of  claim 1 , wherein the first set of switches is open when the second set of switches is closed. 
     
     
         7 . The apparatus of  claim 3 , wherein the voltage offset is resistance of the variable resistor multiplied by the analog current. 
     
     
         8 . A method for generating a voltage offset and output voltage comprising:
 converting an input current to an analog current;   converting a base digital voltage to a base analog voltage;   receiving the analog current and base analog voltage;   selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage; and   selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.   
     
     
         9 . The method of  claim 8 , further comprising providing the base analog voltage to the first buffer when the second set of switches is closed and to the second buffer when the first set of switches is closed. 
     
     
         10 . The method of  claim 8 , further comprising providing voltage output from the first buffer and the second buffer a variable resistor controlled by a range control device. 
     
     
         11 . The method of  claim 10 , further comprising combining output from the variable resistor with the analog current to form a feedback sum. 
     
     
         12 . The method of  claim 11 , further comprising providing the feedback sum to the first buffer when the first set of switches is closed and to the second buffer when the second set of switches is closed. 
     
     
         13 . The method of  claim 8 , wherein the first set of switches is open when the second set of switches is closed. 
     
     
         14 . The method of  claim 10 , wherein the voltage offset is resistance of the variable resistor multiplied by the analog current. 
     
     
         15 . An apparatus for generating a voltage offset and output voltage comprising:
 means for converting an input current to an analog current;   means for converting a base digital voltage to a base analog voltage;   means for receiving the analog current and base analog voltage; and   means for selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage and selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.   
     
     
         16 . The apparatus of  claim 15 , further comprising means for providing the base analog voltage to the first buffer when the second set of switches is closed and to the second buffer when the first set of switches is closed. 
     
     
         17 . The apparatus of  claim 15 , further comprising means for providing voltage output from the first buffer and the second buffer a variable resistor controlled by a range control device. 
     
     
         18 . The apparatus of  claim 17 , further comprising means for combining output from the variable resistor with the analog current to form a feedback sum. 
     
     
         19 . The apparatus of  claim 18 , further comprising means for providing the feedback sum to the first buffer when the first set of switches is closed and to the second buffer when the second set of switches is closed. 
     
     
         20 . The apparatus of  claim 15 , wherein the first set of switches is open when the second set of switches is closed. 
     
     
         21 . The method of  claim 17 , wherein the voltage offset is resistance of the variable resistor multiplied by the analog current. 
     
     
         22 . A non-transitory computer readable media including program instructions which when executed by a processor cause the processor to perform a method for generating a voltage offset and output voltage, the method comprising:
 converting an input current to an analog current;   converting a base digital voltage to a base analog voltage;   receiving the analog current and base analog voltage;   selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage; and   selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.