Semiconductor memory device, and method of controlling the same

Abstract

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

1 - 6 . (canceled) 
     
     
         7 . A method of controlling a dynamic random access memory including dynamic memory cells, comprising:
 outputting a first plurality of control signals to a plurality of lines to put the dynamic random access memory in a low power consumption mode, in which the dynamic memory cells in the dynamic random access memory do not retain data in the low power consumption mode;   keeping at least one signal of the first plurality of control signals to a first voltage to maintain the low power consumption mode;
 outputting a second plurality of control signals to the plurality of lines to put the dynamic random access memory out of the low power consumption mode; and 
   waiting for completion of initialization of the dynamic random access memory during a first period, the initialization being performed in response to the second plurality of control signals,   wherein the dynamic random access memory continues to be supplied with a power supply voltage in the low power consumption mode.   
     
     
         8 . The method of controlling the dynamic random access memory according to  claim 7 , further comprising
 stopping an operation of an internal voltage generator configured to supply an internal voltage to the dynamic memory cells in the low power consumption mode.   
     
     
         9 . The method of controlling the dynamic random access memory according to  claim 7 , further comprising
 stopping a supply of an internal voltage to the dynamic memory cells in the low power consumption mode.   
     
     
         10 . The method of controlling the dynamic random access memory according to  claim 7 , further comprising
 supplying an internal voltage to the dynamic memory cells in response to the outputting the second plurality of control signals, in which the internal voltage is stabilized by the initialization.   
     
     
         11 . The method of controlling the dynamic random access memory according to  claim 7 , wherein
 the first period is equal to or more than 200 micro seconds.   
     
     
         12 . The method of controlling the dynamic random access memory according to  claim 10 , further comprising
 generating the internal voltage by an internal voltage generator.   
     
     
         13 . A memory system comprising:
 a dynamic random access memory including dynamic memory cells;   a memory bus; and   a CPU coupled to the dynamic random access memory through the memory bus and configured to control the dynamic random access memory,   wherein the CPU   outputs a first plurality of control signals to the memory bus to put the dynamic random access memory in a low power consumption mode, in which the dynamic memory cells in the dynamic random access memory do not retain data in the low power consumption mode,   keeps at least one signal of the first plurality of control signals to a first voltage to maintain the low power consumption mode,   outputs a second plurality of control signals to the memory bus to put the dynamic random access memory out of the low power consumption mode, and   waits for completion of initialization of the dynamic random access memory during a first period, the initialization being performed in response to the second plurality of control signals, and   wherein the dynamic random access memory continues to be supplied with a power supply voltage in the low power consumption mode.   
     
     
         14 . The memory system according to  claim 13 , wherein
 the CPU controls a non-volatile memory including flash memory cells through the memory bus.   
     
     
         15 . The memory system according to  claim 13 , further comprising
 an internal voltage generator configured to stop a supply of an internal voltage to the dynamic memory cells in the low power consumption mode.   
     
     
         16 . The memory system according to  claim 13 , further comprising
 a voltage line configured to supply an internal voltage to the dynamic memory cells and stop, in the low power consumption mode, a supply of the internal voltage to the dynamic memory cells.   
     
     
         17 . The memory system according to  claim 13 , further comprising
 a voltage line configured to supply an internal voltage to the dynamic memory cells in response to the outputting the second plurality of control signals, in which the internal voltage is stabilized by the initialization.   
     
     
         18 . The memory system according to  claim 13 , wherein
 the first period is equal to or more than 200 micro seconds.