Memory system and method having unidirectional data buses

Abstract

A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.

1 . A computer system, comprising:
 a processor having a processor bus;   an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;   an output device coupled to the processor through the processor bus to allow data to be output from the computer system;   a mass data storage device coupled to the processor through the processor bus to allow data to be read from the mass storage device;   a system controller coupled to the processor through the processor bus, the system controller comprising a memory controller having a first plurality of memory device output terminals and a second plurality of memory device data input terminals;   at plurality of memory devices each having at least one output terminal and at least one input terminal;   a unidirectional downstream bus coupling the memory device output terminals of the memory controller to the at least one input terminal of the memory device, the downstream bus being isolated from the memory device data input terminals of the memory controller and the at least one data output terminal of the memory device; and   a unidirectional upstream bus coupling the at least one data output terminals of the memory device to the memory device data input terminals of the memory controller, the upstream bus being isolated from the memory device output terminals of the memory controller and the input terminals of the memory device.   
     
     
         2 . The computer system of  claim 1  wherein the memory device comprises a plurality of memory banks, each memory bank having an input terminal coupled to the unidirectional downstream bus and an output terminal coupled to the unidirectional upstream bus. 
     
     
         3 . The computer system of  claim 1  wherein the memory device further comprises a write buffer coupled to the input terminal of the memory device, the write buffer being operable to store write data from at least one write request and to couple the write data from the write buffer for storage in the memory device when the memory device is not processing a read request. 
     
     
         4 . The computer system of  claim 3  wherein the memory controller is operable to output a predetermined memory command when the memory device is not processing a read request, the predetermined memory command being coupled to the input terminal of the memory device through the downstream bus, and wherein the memory device is operable to couple the write data from the write buffer for storage in the memory device responsive to the predetermined memory command. 
     
     
         5 . The computer system of  claim 4  wherein the predetermined command comprises a column address strobe command. 
     
     
         6 . The computer system of  claim 1  wherein the memory controller is further operable to couple memory commands and row and column addresses to the output terminals of the memory controller, the memory commands and row and column addresses being coupled to the memory device through the downstream bus. 
     
     
         7 . The computer system of  claim 6  wherein the memory device further comprises a command/address register coupled to the input terminal of the memory device, the command/address register being operable to store the memory commands and the row and column addresses coupled to the memory device through the downstream bus. 
     
     
         8 . The computer system of  claim 1  wherein the memory device comprises a dynamic random access memory device. 
     
     
         9 . The computer system of  claim 7  wherein the memory controller is further operable to output a clock signal, and the memory device comprises a synchronous dynamic random access memory device and includes a clock input terminal, the memory system further comprising a clock signal line coupling the clock signal from the memory controller to the clock input of the memory device.