Semiconductor devices including source/drain stressors and methods of manufacturing the same

Abstract

A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate;   gate spacers on sidewalls of the gate structure;   a silicon germanium pattern including an impurity region on a side of the gate structure, wherein the silicon germanium pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion, and wherein the facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers;   a blocking insulating layer extending conformally on the silicon germanium pattern and the gate spacers; and   an insulating wing pattern in the concave portion on the blocking insulating layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the insulating wing pattern comprises an insulating material having an etching rate different from that of the blocking insulating layer under a predetermined etching condition. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the blocking insulating layer has a thickness in range of 10 Å to 30 Å. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a portion of the silicon germanium pattern is disposed in a recess portion in the semiconductor substrate. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the insulating wing pattern covers a portion of the blocking insulating layer in the concave portion and exposes blocking insulating layer outside of the concave portion. 
     
     
         6 . A semiconductor device, comprising:
 a semiconductor substrate including an NMOSFET region and a PMOSFET region;   a first gate structure and first spacers on sidewalls of the first gate structure in the NMOSFET region;   a second gate structure and second spacers on sidewalls of the second gate structure in the PMOSFET region;   a silicon pattern on a side of the first gate structure in the NMOSFET region, wherein the silicon pattern includes a first protruded portion having a top surface higher than a bottom surface of the first gate structure and a first facet in the first protruded portion, and wherein the first facet is slanted at a first predetermined angle with respect to an upper surface of the semiconductor substrate and forms a first concave portion with one of the first spacers;   a silicon germanium pattern on a side of the second gate structure in the PMOSFET region, wherein the silicon germanium pattern includes a second protruded portion having a top surface higher than a bottom surface of the second gate structure and a second facet in the second protruded portion, and wherein the second facet is slanted at a second predetermined angle with respect to the upper surface of the semiconductor substrate and forms a second concave portion with one of the second spacers;   a blocking insulating layer extending conformally on the silicon germanium pattern and the second spacers;   a first insulating wing pattern in the first concave portion; and   a second insulating wing pattern in the second concave portion.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the first and second insulating wing patterns comprise an insulating material having an etching rate different from that of the blocking insulating layer under a predetermined etching condition. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the silicon pattern comprises an N type impurity region and the silicon germanium pattern comprises a P type impurity region. 
     
     
         9 . The semiconductor device of  claim 6 , further comprising a first metallic silicide pattern on the silicon pattern and a second metallic silicide pattern on the silicon germanium pattern, and wherein the first and second metallic silicide patterns contact the silicon pattern and the silicon germanium pattern respectively. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the first and second metallic silicide patterns comprise bottom surfaces higher than the bottom surfaces of the first and second gate structures respectively. 
     
     
         11 . The semiconductor device of  claim 6 , wherein the first gate structure includes a first gate electrode and the second gate structure includes a second gate electrode, and wherein the first and second electrodes comprise a metal. 
     
     
         12 . The semiconductor device of  claim 6 , wherein the first and the second insulating wing patterns comprise an identical material. 
     
     
         13 . The semiconductor device of  claim 6 , wherein the first insulating wing pattern directly contacts the one of the first spacers and the first facet of the silicon pattern, and wherein a portion of the blocking insulating layer in the second concave portion extends between the second insulating wing pattern and the one of the second spacers and between the second insulating wing pattern and the second facet of the silicon germanium pattern. 
     
     
         14 . The semiconductor device of  claim 6 , wherein the blocking insulating layer comprises silicon nitride and the first and second insulating wing patterns comprise silicon oxide. 
     
     
         15 . The semiconductor device of  claim 6 , wherein the blocking insulating layer has a thickness in range of 10 Å to 30 Å. 
     
     
         16 . A method of fabricating an integrated circuit device, comprising:
 forming a gate structure comprising a gate insulating layer and a gate electrode on a substrate;   forming a gate spacer on a sidewall of the gate structure;   forming a stressor pattern on a side of the gate structure, wherein the stressor pattern includes a raised portion extending above an upper surface of the substrate, and wherein a sidewall of the raised portion of the stressor pattern and a sidewall of the gate spacer form an opening;   forming a blocking insulating layer on the stressor pattern, the gate spacer and the gate structure; and   forming an insulating wing pattern in the opening on the blocking insulating layer, wherein a portion of the blocking insulating layer in the opening extends between the insulating wing pattern and the stressor pattern and between the insulating wing pattern and the gate spacer.   
     
     
         17 . The method of  claim 16 , wherein the insulating wing pattern exposes a portion of the blocking insulating layer formed on an upper surface of the stressor pattern, and the method further comprises implanting dopants into the stressor pattern through the blocking insulating layer formed on the upper surface of the stressor pattern while the insulating wing pattern being exposed. 
     
     
         18 . The method of  claim 16 , wherein forming the blocking insulating layer comprises forming the blocking insulating layer having a thickness in range of 10 Å to 30 Å. 
     
     
         19 . The method of  claim 16 , wherein forming the insulating wing pattern comprises forming the insulating wing pattern comprising an insulating material, which has etch selectivity relative to the blocking insulating layer. 
     
     
         20 . The method of  claim 16 , further comprising:
 forming an insulating interlayer covering the insulating wing pattern and the stressor pattern; and   forming a contact pattern through the insulating interlayer and the blocking insulating layer formed on an upper surface of the stressor pattern, wherein the contact pattern contacts the stressor pattern and a lower portion of the contact pattern is surrounded by the blocking insulating layer.