Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. Also, because it does not have to consider step coverage based on the aspect ratio of openings, there is no limitation in the method of depositing a metal layer. Therefore, productivity may be improved.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate including an active region;   an insulation layer formed over the substrate;   a plurality of openings formed in the insulation layer;   a plurality of contact plugs filling the plurality of openings; and   a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a plurality of trenches formed by etching the silicide layer and the substrate; and   a plurality of buried gates formed in the plurality of trenches.   
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a conductive line formed between the contact plugs, where the conductive line includes a conductive layer; and   a silicide layer formed over the substrate and between the substrate and the conductive layer in order to cover a bottom of the conductive layer.   
     
     
         4 . The semiconductor device of  claim 2 , wherein the buried gates include:
 a gate electrode filling a portion of each trench of the trenches; and   a sealing layer filling a remaining portion of each trench over the gate electrode.   
     
     
         5 . A method for fabricating a semiconductor device, comprising:
 forming a substrate including a plurality of active regions;   forming a silicide layer over the substrate including the plurality of active regions;   forming a plurality of trenches by etching the silicide layer and the substrate;   forming a plurality of buried gates in the plurality of trenches;   forming an inter-layer dielectric layer that covers a profile of the substrate; and   forming a plurality openings that expose the silicide layer by selectively etching the inter-layer dielectric layer.   
     
     
         6 . The method of  claim 5 , further comprising:
 forming a plurality of contact plugs by filling the openings with a conductive material,   wherein the plurality of openings are formed in a hole type.   
     
     
         7 . The method of  claim 5 , further comprising:
 forming a plurality of spacers on sidewalls of the openings;   forming a conductive layer that fills a portion of each opening; and   forming an insulation layer that fills a remaining portion of each opening over the conductive layer,   wherein the openings are formed in a line type.   
     
     
         8 . A method for fabricating a semiconductor device, comprising:
 forming an isolation layer for defining a plurality of active regions in each region of a substrate having a first region and a second region;   forming a silicide layer over the substrate including the active regions of the first region;   forming a plurality of trenches by etching the silicide layer and the substrate of the first region;   forming a plurality of buried gates in the plurality of trenches;   forming an inter-layer dielectric layer on a profile of the substrate; and   forming a plurality of openings that expose the silicide layer by selectively etching the inter-layer dielectric layer.   
     
     
         9 . The method of  claim 8 , wherein the first region is a cell region, and the second region is a peripheral region. 
     
     
         10 . The method of  claim 8 , wherein the forming of the silicide layer includes:
 forming a barrier layer that covers the substrate of the second region;   forming a metal layer on the profile of the substrate including the barrier layer;   forming a silicide layer on the surface of the active regions of the first region by performing a thermal treatment; and   removing the metal layer that remains unreacted and the barrier layer.   
     
     
         11 . The method of  claim 8 , further comprising:
 forming a protective layer on the surface of the substrate before the trenches are formed.   
     
     
         12 . The method of  claim 8 , further comprising:
 forming a plurality of contact plugs by filling the openings with a conductive material,   wherein the openings are formed in a hole type.   
     
     
         13 . The semiconductor device of  claim 8 , further comprising:
 forming a plurality of spacers on sidewalls of the openings;   forming a conductive layer that fills a portion of each opening; and   forming an insulation layer that fills a remaining portion of each opening over the conductive layer,   wherein the openings are formed in a line type.   
     
     
         14 . A semiconductor device, comprising:
 a substrate including a plurality of active regions;   an inter-layer dielectric layer formed over the substrate; and   a plurality of openings formed in the inter-layer dielectric layer;   a plurality of contact plugs filling the plurality of openings; and   a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug.   
     
     
         15 . The semiconductor device of  claim 14 , further comprising:
 a plurality of trenches formed by etching the silicide layer and the substrate; and   a plurality of buried gates formed in the plurality of trenches.   
     
     
         16 . The semiconductor device of  claim 14 , further comprising:
 a conductive line formed between the contact plugs, where the conductive line includes a conductive layer; and   a silicide layer formed over the substrate and between the substrate and the conductive layer in order to cover a bottom of the conductive layer.   
     
     
         17 . The semiconductor device of  claim 15 , wherein the buried gates include:
 a gate electrode filling a portion of each trench of the trenches; and   a sealing layer filling a remaining portion of each trench over the gate electrode.