Bridging device having a frequency configurable clock domain

Abstract

A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

What is claimed is: 
     
         1 . A method for controlling a selected memory device of a plurality of discrete memory devices, comprising:
 receiving a global command synchronously with a system clock;   generating a memory clock using one of at least two clock divide ratios of the system clock;   converting the global command into a local command to be synchronized with the memory clock; and   issuing the local command from one of a plurality of sets of dedicated local input/outputs to the selected memory device.   
     
     
         2 . The method of  claim 1 , further including receiving information at the one of the plurality of sets of dedicated local input/outputs from the selected memory device. 
     
     
         3 . The method of  claim 2 , wherein receiving information includes receiving and storing read data in memory from the selected memory device in response to the local command executed by the selected memory device. 
     
     
         4 . The method of  claim 3 , wherein receiving and storing read data includes providing the read data at a first data rate corresponding to a frequency of the memory clock for writing to the memory. 
     
     
         5 . The method of  claim 4 , further including providing the read data from the memory at a second data rate corresponding to a frequency of the system clock. 
     
     
         6 . The method of  claim 1 , further including receiving and storing write data in memory after receiving the global command. 
     
     
         7 . The method of  claim 6 , wherein issuing the local command includes providing the write data stored in the memory to the selected memory device at a first data rate corresponding to a frequency of the memory clock. 
     
     
         8 . The method of  claim 7 , wherein receiving and storing write data includes providing the write data to the memory at a second data rate corresponding to a frequency of the system clock. 
     
     
         9 . The method of  claim 1 , wherein generating includes receiving and storing a frequency divide ratio code. 
     
     
         10 . The method of  claim 9 , wherein generating further includes controlling a frequency controller to change a divide ratio of the system clock to a ratio corresponding to the frequency divide ratio code. 
     
     
         11 . The method of  claim 10 , wherein the frequency divide ratio code includes multiple bits corresponding to integer and non-integer divide ratios. 
     
     
         12 . The method of  claim 11 , wherein generating further includes
 dividing the system clock by different integer and non-integer divide ratios to provide intermediate clock signals, and   passing one of the intermediate clock signals as the memory clock in response to the frequency divide ratio code corresponding to any one of the different integer and non-integer divide ratios.   
     
     
         13 . The method of  claim 9 , wherein generating includes decoding the frequency divide ratio code to generate one of a plurality ratio selector signals corresponding to one of the at least two clock divide ratios. 
     
     
         14 . The method of  claim 13 , wherein generating further includes
 providing first intermediate clock signals on first edges of the system clock and second intermediate clock signals on second edges of the system clock, where each of the first intermediate clock signals and the second intermediate clock signals have a period set by the one of the plurality of ratio selector signals, and   logically combining selected first intermediate clock signals and selected second intermediate clock signals to provide the memory clock having a frequency corresponding to the system clock divided by the one of the at least two clock divide ratios.   
     
     
         15 . A method for controlling a plurality of discrete memory devices, comprising:
 receiving global commands synchronously with a system clock;   generating a memory clock using one of at least two clock divide ratios of the system clock;   converting the global commands into local commands to be synchronized with the memory clock; and,   issuing the local commands from sets of dedicated local input/outputs each connected to one of the plurality of discrete memory devices.   
     
     
         16 . The method of  claim 15 , wherein generating includes receiving and storing a frequency divide ratio code. 
     
     
         17 . The method of  claim 16 , wherein generating further includes controlling a frequency controller to change a divide ratio of the system clock to a ratio corresponding to the frequency divide ratio code. 
     
     
         18 . The method of  claim 17 , wherein generating further includes
 dividing the system clock by different integer and non-integer divide ratios to provide intermediate clock signals, and   passing one of the intermediate clock signals as the memory clock in response to the frequency divide ratio code corresponding to any one of the different integer and non-integer divide ratios.   
     
     
         19 . The method of  claim 16 , wherein generating includes decoding the frequency divide ratio code to generate one of a plurality ratio selector signals corresponding to one of the at least two clock divide ratios. 
     
     
         20 . The method of  claim 19 , wherein generating further includes
 providing first intermediate clock signals on first edges of the system clock and second intermediate clock signals on second edges of the system clock, where each of the first intermediate clock signals and the second intermediate clock signals have a period set by the one of the plurality of ratio selector signals, and   logically combining selected first intermediate clock signals and selected second intermediate clock signals to provide the memory clock having a frequency corresponding to the system clock divided by the one of the at least two clock divide ratios.   
     
     
         21 . The method of  claim 15 , further including receiving and storing write data. 
     
     
         22 . The method of  claim 21 , wherein receiving and storing write data includes providing the write data to a memory at a first data rate corresponding to a frequency of the system clock, and issuing the local commands includes providing the write data stored in the memory to the plurality of discrete memory devices at a second data rate corresponding to a frequency of the memory clock. 
     
     
         23 . The method of  claim 22 , further including receiving read data from each of the plurality of discrete memory devices at each of the sets of dedicated local input/outputs respectively. 
     
     
         24 . The method of  claim 23 , wherein receiving read data includes storing the read data in the memory at the second data rate. 
     
     
         25 . The method of  claim 24 , further including providing the read data from the memory at the first data rate. 
     
     
         26 . A system comprising:
 a multi-chip package that includes:
 a) a plurality of discrete memory devices; 
 b) a bridge device for controlling the discrete memory devices, the bridge device including:
 i) a first clock domain having first logic circuits and first control circuits to operate in synchronization with a memory clock for issuing local commands to the discrete memory devices; 
 ii) a frequency controller for generating the memory clock using one of at least two clock divide ratios of a system clock to be provided to the bridge device, the frequency controller including a register for receiving a frequency divide code to control selection of the one of at least two clock divide ratios; and 
 iii) a second clock domain having second logic circuits and second control circuits to operate in synchronization with the system clock for converting a global command to be received synchronously with the system clock into a local command synchronized with the memory clock. 
 
   
     
     
         27 . The system as claimed in  claim 26 , wherein the each of the discrete memory devices is a flash memory device. 
     
     
         28 . The system as claimed in  claim 26 , wherein the each of the discrete memory devices is a NAND flash memory device.