US2013315310A1PendingUtilityA1

Delta frame buffers

Assignee: BROADCOM CORPPriority: Jun 25, 2003Filed: May 9, 2013Published: Nov 28, 2013
Est. expiryJun 25, 2023(expired)· nominal 20-yr term from priority
H04N 19/50H04N 19/427H04N 19/00569
51
PatentIndex Score
0
Cited by
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References
0
Claims

Abstract

Presented herein is a system and method for reducing the total size of the frame buffer portion of a decoding circuit. The reduction in size is possible because first portions of B-pictures are displayed while second portions occurring later in the raster order are decoded. The foregoing allows the second portions occurring later in the raster order to overwrite third portions of the picture that have already been displayed. As a result, the frame buffer for providing the frame from a decoder to the display engine need only store the portion that is being displayed and the portion that is being decoded.

Claims

exact text as granted — not AI-modified
1 - 17 . (canceled) 
     
     
         18 . A method, comprising:
 decoding a first portion of a frame;   writing the first portion of the frame to a memory; and   displaying the first portion of the frame while decoding a second portion of the frame and writing the second portion of the frame to the memory.   
     
     
         19 . The method of  claim 18 , comprising:
 displaying the second portion of the frame while decoding a third portion of the frame; and   writing the third portion of the frame to the memory over the first portion of the frame.   
     
     
         20 . The method of  claim 19 , comprising:
 displaying the third portion of the frame while decoding a forth portion of the frame; and   writing the forth portion of the frame to the memory over the second portion of the frame.   
     
     
         21 . The method of  claim 18 , wherein decoding the first and second portions of the frame comprises bidirectionally predicting the first and second portions of the frame based on other frames in a group of pictures. 
     
     
         22 . The method of  claim 18 , wherein the frame comprises a progressive frame. 
     
     
         23 . The method of  claim 18 , wherein:
 the memory comprises a prediction frame buffer and a delta frame buffer; and   writing the first portion of the frame to the memory comprises writing the first portion of the frame to the delta frame buffer.   
     
     
         24 . The method of  claim 23 , wherein:
 the delta frame buffer is about half the size of the prediction frame buffer;   writing the first portion of the frame to the delta frame buffer comprises writing the first portion of the frame to a first region of the delta frame buffer; and   writing the second portion of the frame to the delta frame buffer comprises writing the second portion of the frame to a second region of the delta frame buffer.   
     
     
         25 . A circuit, comprising:
 a memory comprising a prediction frame buffer and a delta frame buffer;   a decoder that decodes a first portion of a frame;   a controller that writes the first portion of the frame to the delta frame buffer; and   a display engine that displays the first portion of the frame while the decoder decodes a second portion of the frame.   
     
     
         26 . The circuit of  claim 25 , wherein:
 while the display engine displays the first portion of the frame, the controller writes the second portion of the frame to the delta frame buffer.   
     
     
         27 . The circuit of  claim 25 , wherein:
 the display engine displays the second portion of the frame while the decoder decodes a third portion of the frame; and   the controller writes the third portion of the frame to the delta frame buffer over the first portion of the frame.   
     
     
         28 . The circuit of  claim 27 , wherein:
 the display engine displays the third portion of the frame while the decoder decodes a forth portion of the frame; and   the controller writes the forth portion of the frame to the delta frame buffer over the second portion of the frame.   
     
     
         29 . The circuit of  claim 25 , wherein the decoder bidirectionally predicts the first and second portions of the frame based on other frames in a group of pictures. 
     
     
         30 . The circuit of  claim 25 , wherein the frame comprises a progressive frame. 
     
     
         31 . The circuit of  claim 25 , wherein:
 the delta frame buffer is about half the size of the prediction frame buffer;   the controller writes the first portion of the frame to a first region of the delta frame buffer; and   the controller writes the second portion of the frame to a second region of the delta frame buffer.   
     
     
         32 . A method, comprising:
 decoding a first portion of a first field;   writing the first portion of the first field to a memory; and   displaying the first portion of the first field while decoding a second portion of the first field and writing the second portion of the first field to the memory.   
     
     
         33 . The method of  claim 32 , comprising:
 displaying the second portion of the first field while decoding a first portion of a second field; and   writing the first portion of the second field to the memory over the first portion of the first field.   
     
     
         34 . The method of  claim 33 , comprising:
 displaying the first portion of the second field while decoding a second portion of the second field; and   writing the second portion of the second field to the memory over the second portion of the first field.   
     
     
         35 . The method of  claim 32 , wherein decoding the first and second portions of the first field comprises bidirectionally predicting the first and second portions of the first field based on other fields in a group of pictures. 
     
     
         36 . The method of  claim 32 , wherein the first field comprises a field of a progressive frame. 
     
     
         37 . The method of  claim 32 , wherein:
 the memory comprises a prediction frame buffer and a delta frame buffer; and   writing the first portion of the first field to the memory comprises writing the first portion of the first field to the delta frame buffer.   
     
     
         38 . The method of  claim 37 , wherein:
 the delta frame buffer is about half the size of the prediction frame buffer;   writing the first portion of the first field to the delta frame buffer comprises writing the first portion of the first field to a first region of the delta frame buffer; and   writing the second portion of the first field to the delta frame buffer comprises writing the second portion of the first field to a second region of the delta frame buffer.

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