US2013314980A1PendingUtilityA1

Row-decoder circuit and method with dual power systems

Assignee: QUALCOMM INCPriority: Jan 21, 2011Filed: Jul 30, 2013Published: Nov 28, 2013
Est. expiryJan 21, 2031(~4.5 yrs left)· nominal 20-yr term from priority
G11C 11/1673G11C 11/1653G11C 11/1693G11C 11/1659G11C 11/1675G11C 8/10G11C 11/1657G11C 8/08
44
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Claims

Abstract

A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method, comprising:
 sharing charge, during a first memory operation, between a word line and a common node of a memory to obtain a first voltage level at the word line;   performing the first memory operation using the first voltage level; and   performing a second memory operation with a second voltage level.   
     
     
         2 . The method of  claim 1 , in which the first memory operation includes a read operation of a magnetic random access memory (MRAM). 
     
     
         3 . The method of  claim 1 , further comprising:
 coupling a plurality of unit row decoders to the common node to provide power at the first voltage level for the plurality of row decoders; and   turning off power from a first voltage driver and a second voltage driver during the charge sharing to obtain the first voltage level.   
     
     
         4 . The method of  claim 1 , further comprising:
 adjusting the first voltage level to achieve a predefined voltage level during the first memory operation.   
     
     
         5 . The method of  claim 1 , comprising
 providing a read line control signal to control a first voltage driver of the memory, the first voltage driver coupled to the common node; and   providing a delayed read line control signal to control a second voltage driver of the memory, the second voltage driver coupled to the common node;   in which the first memory operation includes turning off power from the first voltage driver and the second voltage driver by de-asserting the delayed read line control signal for a delay period before asserting the read line control signal.   
     
     
         6 . The method of  claim 5 , further comprising:
 floating the common node during the delay period; and   pre-charging the common node by charge sharing between a capacitive coupling of the common node and a capacitive coupling of the word line.   
     
     
         7 . The method of  claim 1 , further comprising performing the first and second memory operations in at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit. 
     
     
         8 . A memory, comprising:
 a voltage driver coupled to a common node and configured for supplying a word line voltage to a word line of the memory;   a first capacitive coupling coupled to the common node;   a second capacitive coupling coupled to the word line;   a word line driver transistor coupled between the first capacitive coupling and the second capacitive coupling; and   control circuitry configured to control the voltage driver to float the common node to obtain a first voltage from a charge shared between the first capacitive coupling and the second capacitive coupling, the first voltage being applied during a first type of memory access operation.   
     
     
         9 . The memory of  claim 8 , integrated into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit. 
     
     
         10 . A method, comprising the steps of:
 sharing charge, during a first memory operation, between a word line and a common node of a magnetic random access memory (MRAM) to obtain a first voltage at the word line;   performing the first memory operation using the first voltage; and   performing a second memory operation with a second voltage.   
     
     
         11 . The method of  claim 10 , further comprising the step of performing the first and second memory operations in at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit. 
     
     
         12 . A memory, comprising:
 a first voltage driving means, coupled to a common node, for supplying a word line voltage to a word line of the memory;   a second voltage driver means, coupled to the common node, for supplying a core voltage to the word line of the memory; and   control means for controlling the first voltage driving means and the second voltage driving means for providing a delay period between turning off the first voltage driving means and turning on the second voltage driving means with respect to memory access operations.   
     
     
         13 . The memory of  claim 12 , integrated into at least one of a mobile phone, a set, top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a. fixed location data unit. 
     
     
         14 . A memory, comprising:
 a voltage driving means, coupled to a common node, for supplying a word line voltage to a word line of the memory;   a first capacitive means, coupled to the common node;   a second capacitive means, coupled to the word line;   a word line driving means, coupled between the first capacitive coupling and the second capacitive coupling; and   control means for controlling the voltage driving means to float the common node to obtain a first voltage from a charge shared between the first capacitive means and the second capacitive means, the first voltage being applied during a first type of memory access operation.   
     
     
         15 . The memory of  claim 14 , integrated into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

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