Semiconductor fuse with enhanced post-programming resistance

Abstract

Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.

What is claimed is: 
     
         1 . A method comprising:
 forming a shallow trench isolation (STI) region in a silicon substrate;   forming a high-κ dielectric layer on the STI region;   forming a metal gate on the high-κ dielectric layer;   forming a polysilicon layer over the metal gate;   performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate; and   forming a silicide on the amorphous silicon layer.   
     
     
         2 . The method according to  claim 1 , comprising forming cathode and anode contacts over opposite ends of the silicide to form a fuse structure having a fuse link between the cathode and anode contacts. 
     
     
         3 . The method according to  claim 1 , comprising implanting xenon for the implantation. 
     
     
         4 . The method according to  claim 3 , comprising performing the implantation at an energy of 80 keV to 150 keV. 
     
     
         5 . The method according to  claim 1 , comprising implanting germanium for the implantation. 
     
     
         6 . The method according to  claim 5 , comprising performing the implantation at an energy of 80 keV to 150 keV. 
     
     
         7 . The method according to  claim 1 , comprising forming the high-K dielectric layer of hafnium oxide and lanthanum and forming the metal gate of titanium nitride. 
     
     
         8 . The method according to  claim 1 , comprising forming nickel silicide for the silicide. 
     
     
         9 . The method according to  claim 1 , comprising breaking up the metal gate into discrete specks of material dispersed at the interface between the amorphous silicon layer and the STI region sufficiently to prevent or limit electrical conduction via the resulting broken-up metal gate. 
     
     
         10 . A passive device comprising:
 a shallow trench isolation (STI) region in a silicon substrate;   an amorphous silicon layer formed on the STI region;   a silicide formed on the amorphous silicon layer; and   cathode and anode contacts over opposite ends of the silicide, wherein the amorphous silicon layer is formed by:   forming a high-κ/metal gate (HKMG) and a polysilicon layer on the STI region;   performing an implantation on the polysilicon layer, wherein the implantation converts the polysilicon into amorphous silicon and concurrently breaks up the HKMG.   
     
     
         11 . The passive device according to  claim 10 , wherein the amorphous silicon layer, silicide, and cathode and anode contacts are configured to form a fuse structure, said fuse structure including a fuse link between the cathode and anode contacts. 
     
     
         12 . The passive device according to  claim 11 , wherein the resulting broken-up HKMG comprises discrete specks of material dispersed at the interface between the amorphous silicon layer and the STI region. 
     
     
         13 . The passive device according to  claim 12 , wherein the specks are sufficiently dispersed to prevent or limit electrical conduction to the contacts. 
     
     
         14 . The passive device according to  claim 11 , wherein the HKMG includes a first layer of hafnium oxide and lanthanum formed on the shallow trench isolation region, and a second layer of titanium nitride formed on the first layer. 
     
     
         15 . The passive device according to  claim 11 , wherein the implantation is performed by implanting xenon. 
     
     
         16 . The passive device according to  claim 15 , wherein the implantation is performed at an energy of 80 keV to 150 keV. 
     
     
         17 . The passive device according to  claim 11 , wherein the implantation is performed by implanting germanium. 
     
     
         18 . The passive device according to  claim 17 , wherein the implantation is performed at an energy of 80 keV to 150 keV. 
     
     
         19 . The passive device according to  claim 11 , wherein the silicide comprises nickel silicide. 
     
     
         20 . A method comprising:
 forming a shallow trench isolation (STI) region in a silicon substrate;   forming a high-κ/metal gate (HKMG) comprising a high-x dielectric layer and a titanium nitride (TiN) metal gate on the STI region;   forming a polysilicon layer on the HKMG;   implanting xenon in the polysilicon layer at an energy of 80 keV to 150 keV, wherein the implantation converts the polysilicon to amorphous silicon and breaks up the HKMG and disperses the HKMG material to eliminate electrical conduction across the HKMG;   forming nickel silicide on the amorphous silicon layer; and   forming an anode contact at one end of the nickel silicide and a cathode contact at the other end of the nickel silicide;   wherein the amorphous silicon layer and the nickel silicide form a fuse link between the anode and cathode contacts.