Removal of stressor layer from a spalled layer and method of making a bifacial solar cell using the same

Abstract

A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

1 . A flexible, bifacial solar cell comprising:
 a semiconductor substrate having a thickness less than fifty microns;   an emitter junction formed on a first side of the semiconductor substrate;   a back junction formed on a second side of the semiconductor substrate;   a transparent conductive layer electrically associated with each junction,   a metal contact layer electrically associated with each transparent conductive layer, and   a transparent handle substrate adjoining one of the metal contact layers.   
     
     
         2 . The flexible, bifacial solar cell of  claim 1 , wherein the semiconductor substrate comprises silicon. 
     
     
         3 . A structure comprising:
 a semiconductor substrate;   a flexible handle substrate on a first side of the semiconductor substrate;   a second handle substrate on a second side of the semiconductor substrate;   a stressor layer between the semiconductor substrate and the flexible handle substrate, and   a cleave layer positioned between the stressor layer and the semiconductor substrate, the cleave layer being selectively etchable or dissolvable with respect to the semiconductor substrate and stressor layer.   
     
     
         4 . The structure of  claim 3 , wherein the cleave layer has a lower fracture toughness value (K lc ) than that of the material comprising the semiconductor substrate. 
     
     
         5 . The structure of  claim 3 , wherein the stressor layer is a metal layer. 
     
     
         6 . The structure of  claim 5 , further including a first junction layer on the first side of the semiconductor substrate and between the semiconductor substrate and the cleave layer. 
     
     
         7 . The structure of  claim 6 , further including a second junction layer on the second side of the semiconductor substrate. 
     
     
         8 . The structure of  claim 7 , wherein the second handle substrate is transparent. 
     
     
         9 . The structure of  claim 8 , wherein the semiconductor substrate has a thickness of less than fifty microns. 
     
     
         10 . The structure of  claim 3 , wherein the second handle substrate is transparent. 
     
     
         11 . The structure of  claim 10 , further including an emitter junction on the semiconductor substrate. 
     
     
         12 . The structure of  claim 3 , wherein the cleave layer is laterally recessed with respect to the semiconductor substrate and the stressor layer, the cleave layer being positioned such that a force exerted on the cleave layer through the stressor layer causes spalling through the cleave layer. 
     
     
         13 . The structure of  claim 12 , wherein the stressor layer is a metal layer. 
     
     
         14 . The structure of  claim 13 , wherein the semiconductor substrate comprises silicon. 
     
     
         15 . The structure of  claim 14 , further including an emitter junction on the semiconductor substrate. 
     
     
         16 . The structure of  claim 15 , wherein the second handle substrate is transparent. 
     
     
         17 . The structure of  claim 16 , wherein the semiconductor substrate has a thickness of less than fifty microns. 
     
     
         18 . The structure of  claim 17 , further including a back junction on the semiconductor substrate. 
     
     
         19 . The structure of  claim 12 , further including emitter and back junctions on the semiconductor substrate, and wherein the semiconductor substrate has a thickness of less than fifty microns and the second handle substrate is transparent. 
     
     
         20 . The structure of  claim 19 , wherein the semiconductor substrate comprises silicon.