US2013307507A1PendingUtilityA1
Method and apparatus for zero current detection
Est. expiryMay 19, 2032(~5.8 yrs left)· nominal 20-yr term from priority
G01R 19/175H02M 3/156G01R 19/165H02M 3/135H02M 3/10H02M 1/0009H02M 3/158
48
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Claims
Abstract
This application discusses, among other things, zero current detection. In an example, a circuit for zero current detection can include a compensating circuit and a detecting circuit. The compensating circuit can be configured to feed back a compensating voltage to the detecting circuit according to an output voltage of a DC-DC converting circuit. The detecting circuit can be configured to dynamically adjust an intentional offset voltage according to the compensating voltage, and to perform zero current detection of the DC-DC converting circuit according to the adjusted Voffset.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A circuit for zero current detection, comprising: a compensating circuit and a detecting circuit, wherein
the compensating circuit is configured to feed back a compensating voltage to the detecting circuit according to an output voltage of a Direct Current-Direct Current (DC-DC) converting circuit; and the detecting circuit is configured to dynamically adjust an intentional offset voltage (Voffset) according to the compensating voltage, and perform zero current detection of the DC-DC converting circuit according to the adjusted Voffset.
2 . The circuit for zero current detection according to claim 1 , wherein the compensating circuit is configured to feed, when the DC-DC converting circuit is a BUCK circuit, the output voltage of the BUCK circuit serving as the compensating voltage, back to the detecting circuit.
3 . The circuit for zero current detection according to claim 2 , wherein the compensating circuit comprises a PMOS P 31 , a PMOS P 32 , a PMOS P 33 , a switch S 31 , a switch S 32 , a switch S 33 , a current source Q 31 , a NMOS N 31 , a NMOS N 32 , a resistor R 31 , and a resistor R 32 , wherein the PMOS P 31 and the PMOS P 32 are in cascode connection, with the source of the PMOS P 31 and the source of the PMOS P 32 connected to the input voltage Vin of the BUCK circuit, the drain and the source of the PMOS P 31 are connected, and connected together to the drains of the NMOS N 31 and the NMOS N 32 ; the drain of the PMOS P 32 is connected to Voffset via the switch S 31 ; the gate of the PMOS P 33 is connected to the source of the NMOS N 31 and the gate of the NMOS N 32 , and connected to the output voltage Vout of the BUCK circuit, the drain of the PMOS P 33 is grounded, the source of the PMOS P 33 is connected to the negative electrode of the current source Q 31 and the gate of the NMOS N 31 ; the source of the NMOS N 31 is connected to the resistor R 31 ; the source of the NMOS N 32 is connected to the resistor R 32 ; the positive electrode of the current source Q 31 is connected to the input voltage Vin; the resistor R 31 is grounded via the switch S 32 ; the resistor R 32 is grounded via the switch S 33 .
4 . The circuit for zero current detection according to claim 3 , wherein the detecting circuit comprises a switch S 34 , a switch S 35 , a switch S 36 , a switch S 37 , a PMOS P 34 , a PMOS P 35 , a PMOS P 36 , a NMOS N 33 , a NMOS N 34 , a NMOS N 35 , a NMOS N 36 , a current source Q 32 , and a capacitor CS 31 , wherein one end of the switch S 34 is connected to a switch node SW, the other end of the switch S 34 is connected to the negative electrode of the capacitor CS 31 and the switch S 35 ; the other end of the switch S 35 is grounded; the positive electrode of the capacitor CS 31 is connected to the gates of the PMOS P 34 and the NMOS N 33 ; the source of the PMOS P 34 is connected to the negative electrode of the current Source Q 32 , the drain of the PMOS P 34 is connected to the drain of the NMOS N 33 , and connected to the gates of the PMOS P 35 and the NMOS N 35 ; the positive electrode of the current source Q 32 is connected to the input voltage Vin; the source of the NMOS N 33 is connected to the compensating circuit and the drain of the NMOS N 34 , and connected to the ground via the switch S 37 , the switch S 36 is connected between the gate and the drain of the NMOS N 33 ; the drain voltage of the NMOS N 34 is Voffset, the source of the NMOS N 34 is grounded, the gate of the NMOS N 34 is connected to the input voltage Vin; the PMOS P 35 and the NMOS N 35 , the PMOS P 36 and the NMOS N 36 are connected to be two inverters, the drains of the PMOS P 36 and the NMOS N 36 are output of the circuit for zero current detection.
5 . The circuit for zero current detection according to claim 4 , wherein when the circuit for zero current detection enters a sampling state, the switch S 31 , the switch S 32 , the switch S 33 , the switch S 35 , and the switch S 36 are closed, and the switch S 34 and the switch S 37 are open, the output voltage Vout is converted into the current on the resistor R 31 and the current on the resistor R 32 , the current on the resistor R 31 is I 1 , the current on the resistor R 32 is I 2 , the current of the drain of the PMOS P 32 obtained by mirroring is Ic=I 1 +I 2 , the product of Ic and the on resistance Ron of the NMOS N 34 is the compensating voltage, which is fed back to the drain of the PMOS P 32 , to adjust Voffset, the adjusted Voffset is:
V
offset
=
R
on
(
I
0
+
I
c
)
=
R
on
(
I
0
+
K
I
1
+
K
I
2
)
=
R
on
(
I
0
+
K
V
out
+
V
gsp
-
V
gsn
1
R
31
+
K
V
out
-
V
gsn
2
R
32
wherein, I 0 is the current provided by the current source Q 32 ; K is the current mirroring ratio of the current mirror formed of the PMOS P 31 and the PMOS P 32 ; Vgsp is the source-gate voltage of the PMOS P 33 ; Vgsn 1 is the gate-source voltage of the NMOS N 31 ; Vgsn 2 is the gate-source voltage of the NMOS N 32 .
6 . The circuit for zero current detection according to claim 5 , wherein when the circuit for zero current detection enters a comparing state, the switch S 31 , the switch S 32 , the switch S 33 , the switch S 35 , and the switch S 36 are open, and the switch S 34 and the switch S 37 are closed, when the voltage of SW equals the negative of the adjusted Voffset, the drains of the PMOS P 36 and the NMOS N 36 output a high level.
7 . The circuit for zero current detection according to claim 1 , wherein the compensating circuit is configured to feed, when the DC-DC converting circuit is a BOOST circuit, the difference between the input voltage and the output voltage of the BOOST circuit serving as the compensating voltage, back to the detecting circuit.
8 . The circuit for zero current detection according to claim 7 , wherein the compensating circuit comprises a NMOS N 51 , a NMOS N 52 , a NMOS N 53 , a switch S 51 , a switch S 52 , a switch S 53 , a current source Q 51 , a PMOS P 51 , a PMOS P 52 , a resistor R 51 , and a resistor R 52 , wherein the NMOS N 51 and the NMOS N 52 are in cascode connection, with the source of the NMOS N 51 and the source of the NMOS N 52 being grounded, the drain and the gate of the NMOS N 51 are connected together to the drains of the PMOS P 51 and the PMOS P 52 ; the drain of the NMOS N 52 is connected to Voffset via the switch S 51 ; the gate of the NMOS N 53 is connected to the gate of the PMOS P 51 and the source of the PMOS P 52 , and connected to the input voltage Vin of the BOOST circuit, the drain of the NMOS N 53 is connected to the output voltage Vout of the BOOST circuit, the source of the NMOS N 53 is connected to the positive electrode of the current source Q 51 and the gate of the PMOS P 52 ; the source of the PMOS P 51 is connected to the resistor R 52 ; the source of the PMOS P 52 is connected to the resistor R 51 ; the negative electrode of the current source Q 51 is grounded; the resistor R 51 is connected to the output voltage Vout via the switch S 52 ; the resistor R 52 is connected to the output voltage Vout via the switch S 53 .
9 . The circuit for zero current detection according to claim 8 , wherein the detecting circuit comprises a switch S 54 , a switch S 55 , a switch S 56 , a switch S 57 , a PMOS P 53 , a PMOS P 54 , a PMOS P 55 , a PMOS P 56 , a NMOS N 54 , a NMOS N 55 , a NMOS N 56 , a current source Q 52 , and a capacitor CS 51 , wherein one end of the switch S 54 is connected to a supply voltage VDD, the other end of the switch S 54 is connected to the drain of the PMOS P 53 ; the gate of the PMOS P 53 is grounded, the source of the PMOS P 53 is connected to the supply voltage VDD, the drain of the PMOS P 53 is connected to the compensating circuit and the source of the PMOS P 54 ; one end of the switch S 55 is connected to SW, the other end of the switch S 55 is connected to the negative electrode of the capacitor CS 51 , and connected to the output voltage Vout via the switch S 57 ; the positive electrode of the capacitor CS 51 is connected to the gates of the PMOS P 54 and the NMOS N 54 ; the switch S 56 is connected between the gate and the drain of the PMOS P 54 , the source of the PMOS P 54 is connected to the compensating circuit, the source voltage being Voffset; the drains of the NMOS N 54 and the PMOS P 54 are connected together to the gates of the PMOS P 55 and the NMOS N 55 , the source of the NMOS N 54 is connected to the positive electrode of the current source Q 52 ; the negative electrode of the current source Q 52 is grounded; the PMOS P 55 and the NMOS N 55 , the PMOS P 56 and the NMOS N 56 are connected to be two inverters, the drains of the PMOS P 56 and the NMOS N 56 are the output of the circuit for zero current detection.
10 . The circuit for zero current detection according to claim 9 , wherein when the circuit for zero current detection enters a sampling state, the switch S 51 , the switch S 52 , the switch S 53 , the switch S 56 , and the switch S 57 are closed, and the switch S 54 and the switch S 55 are open, the difference between the output voltage Vout and the input voltage Vin is converted into the current on the resistor R 51 and the current on the resistor R 52 , the current on the resistor R 51 is I 2 , the current on the resistor R 52 is I 1 , the current of the drain of the NMOS N 52 obtained by mirroring is Ic=I 1 +I 2 , the product of Ic and the on resistance Ron of the PMOS P 53 is the compensating voltage, which is fed back to the source of the PMOS P 54 , to adjust Voffset.
11 . The circuit for zero current detection according to claim 10 , wherein when the circuit for zero current detection enters a comparing state, the switch S 51 , the switch S 52 , the switch S 53 , the switch S 56 , and the switch S 57 are open, and the switch S 54 and the switch S 55 are closed, and when the voltage of SW equals the sum of the output voltage Vout of the BOOST circuit and the adjusted Voffset, the drains of the PMOS P 56 and the NMOS N 56 output a high level.
12 . A voltage converting circuit, comprising: a BUCK circuit and a circuit for zero current detection, wherein
the BUCK circuit is configured to lower a DC voltage via a switch device, to generate an output voltage; and the zero current detection circuit is configured to dynamically adjust Voffset according to the output voltage, and perform zero current detection of the BUCK circuit according to the adjusted Voffset.
13 . The voltage converting circuit according to claim 12 , wherein the circuit for zero current detection comprises a compensating circuit and a detecting circuit, wherein
the compensating circuit is configured to feed back a compensating voltage to the detecting circuit according to the output voltage of the BUCK circuit; and the detecting circuit is configured to dynamically adjust Voffset according to the compensating voltage, and perform zero current detection of the BUCK circuit according to the adjusted Voffset.
14 . The voltage converting circuit according to claim 13 , wherein the compensating circuit comprises a PMOS P 31 , a PMOS P 32 , a PMOS P 33 , a switch S 31 , a switch S 32 , a switch S 33 , a current source Q 31 , a NMOS N 31 , a NMOS N 32 , a resistor R 31 , and a resistor R 32 , wherein the PMOS P 31 and the PMOS P 32 are in cascode connection, and the sources of the PMOS P 31 and the PMOS P 32 are connected to the input voltage Vin of the BUCK circuit, the drain and the source of PMOS P 31 are connected together to the drains of the NMOS N 31 and the NMOS N 32 ; the drain of the PMOS P 32 is connected to Voffset via the switch S 31 ; the gate of the PMOS P 33 is connected to the source of the NMOS N 31 and the gate of the NMOS N 32 , and connected to the output voltage Vout of the BUCK circuit, the drain of the PMOS P 33 is grounded, the source of the PMOS P 33 is connected to the negative electrode of the current source Q 31 and the gate of the NMOS N 31 ; the source of the NMOS N 31 is connected to the resistor R 31 ; the source of the NMOS N 32 is connected to the resistor R 32 ; the positive electrode of the current source Q 31 is connected to the input voltage Vin; the resistor R 31 is grounded via the switch S 32 ; the resistor R 32 is grounded via the switch S 33 .
15 . The voltage converting circuit according to claim 14 , wherein the detecting circuit comprises a switch S 34 , a switch S 35 , a switch S 36 , a switch S 37 , a PMOS P 34 , a PMOS P 35 , a PMOS P 36 , a NMOS N 33 , a NMOS N 34 , a NMOS N 35 , a NMOS N 36 , a current source Q 32 , and a capacitor CS 31 , wherein one end of the switch S 34 is connected to a switch node SW, the other end of the switch S 34 is connected to the negative electrode of the capacitor CS 31 and to the switch S 35 ; the other end of the switch S 35 is grounded; the positive electrode of the capacitor CS 31 is connected to the gates of the PMOS P 34 and the NMOS N 33 ; the source of the PMOS P 34 is connected to the negative electrode of the current source Q 32 , the drain of the PMOS P 34 is connected to the drain of the NMOS N 33 , and connected to the gates of the PMOS P 35 and the NMOS N 35 ; the positive electrode of the current source Q 32 is connected to the input voltage Vin; the source of the NMOS N 33 is connected to the compensating circuit and the drain of the NMOS N 34 , and connected to the ground via the switch S 37 , the switch S 36 is connected between the gate and the drain of the NMOS N 33 ; the drain voltage of the NMOS N 34 is Voffset, the source of the NMOS N 34 is grounded, the gate of the NMOS N 34 is connected to the input voltage Vin; the PMOS P 35 and the NMOS N 35 , the PMOS P 36 and the NMOS N 36 are connected to be two inverters, the drains of the PMOS P 36 and the NMOS N 36 are the output of the circuit for zero current detection.
16 . A voltage converting circuit, comprising a BOOST circuit and a circuit for zero current detection;
the BOOST circuit is configured to boost a DC voltage via a switch device, to generate an output voltage; and the zero current detection circuit is configured to dynamically adjust Voffset according to the output voltage, and perform zero current detection of the BOOST circuit according to the adjusted Voffset.
17 . The voltage converting circuit according to claim 16 , wherein the circuit for zero current detection comprises a compensating circuit and a detecting circuit, wherein
the compensating circuit is configured to feed back a compensating voltage to the detecting circuit according to the output voltage of the BOOST circuit; and the detecting circuit is configured to dynamically adjust Voffset according to the compensating voltage, and perform zero current detection of the BOOST circuit according to the adjusted Voffset.
18 . The voltage converting circuit according to claim 17 , wherein the compensating circuit comprises a NMOS N 51 , a NMOS N 52 , a NMOS N 53 , a switch S 51 , a switch S 52 , a switch S 53 , a current source Q 51 , a PMOS P 51 , a PMOS P 52 , a resistor R 51 , and a resistor R 52 , wherein the NMOS N 51 and the NMOS N 52 are in cascode connection, with the sources of the NMOS N 51 and the NMOS N 52 being grounded, the drain and the gate of the NMOS N 51 are connected together to the drains of the PMOS P 51 and the PMOS P 52 ; the drain of the NMOS N 52 is connected to Voffset via the switch S 51 ; the gate of the NMOS N 53 is connected to the gate of the PMOS P 51 and the source of the PMOS P 52 , and connected to the input voltage Vin of the BOOST circuit, the drain of the NMOS N 53 is connected to the output voltage Vout of the BOOST circuit, the source of the NMOS N 53 is connected to the positive electrode of the current source Q 51 and the gate of the PMOS P 52 ; the source of the PMOS P 51 is connected to the resistor R 52 ; the source of the PMOS P 52 is connected to the resistor R 51 ; the negative electrode of the current source Q 51 is grounded; the resistor R 51 is connected to the output voltage Vout via the switch S 52 ; the resistor R 52 is connected to the output voltage Vout via the switch S 53 .
19 . The voltage converting circuit according to claim 18 , wherein the detecting circuit comprises a switch S 54 , a switch S 55 , a switch S 56 , a switch S 57 , a PMOS P 53 , a PMOS P 54 , a PMOS P 55 , a PMOS P 56 , a NMOS N 54 , a NMOS N 55 , a NMOS N 56 , a current source Q 52 , and a capacitor CS 51 , wherein one end of the switch S 54 is connected to a supply voltage VDD, the other end of the switch S 54 is connected to the drain of the PMOS P 53 ; the gate of the PMOS P 53 is grounded, the source of the PMOS P 53 is connected to the supply voltage VDD, the drain of the PMOS P 53 is connected to the compensating circuit and the source of the PMOS P 54 ; one end of the switch S 55 is connected to SW, the other end of the switch S 55 is connected to the negative electrode of the capacitor CS 51 , and connected to the output voltage Vout via the switch S 57 ; the positive electrode of the capacitor CS 51 is connected to the gates of the PMOS P 54 and the NMOS N 54 ; the switch S 56 is connected between the gate and the drain of the PMOS P 54 , the source of the PMOS P 54 is connected to the compensating circuit, the source voltage being Voffset; the drains of the NMOS N 54 and the PMOS P 54 are connected together to the gates of the PMOS P 55 and the NMOS N 55 , the source of the NMOS N 54 is connected to the positive electrode of the current source Q 52 ; the negative electrode of the current source Q 52 is grounded; the PMOS P 55 and the NMOS N 55 , the PMOS P 56 and the NMOS N 56 are connected to be two inverters, the drains of the PMOS P 56 and the NMOS N 56 are the output of the circuit for zero current detection.
20 . A method for zero current detection, comprising:
feeding back a compensating voltage according to an output voltage of a Direct Current-to-Direct Current DC-DC converting circuit; and dynamically adjusting Voffset according to the compensating voltage, and performing zero current detection of the DC-DC converting circuit according to the adjusted Voffset.
21 . The method for zero current detection according to claim 20 , wherein the DC-DC converting circuit is a BUCK circuit.
22 . The method for zero current detection according to claim 21 , wherein the compensating voltage is the output voltage of the BUCK circuit.
23 . The method for zero current detection according to claim 20 , wherein the DC-DC converting circuit is a BOOST circuit.
24 . The method for zero current detection according to claim 23 , wherein the compensating voltage is the difference of the input voltage and the output voltage of the BOOST circuit.Join the waitlist — get patent alerts
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