Method of manufacturing three-dimensional nanochannel device

Abstract

A method of manufacturing a three-dimensional nanochannel device is provided. In the method, a first insulation layer is formed on a substrate, a first opening is formed in the first insulation layer, and a patterned photoresist is formed on the first insulation layer. The patterned photoresist includes at least one second opening, wherein the second opening is adjacent to the first opening and exposes the first insulation layer. Afterwards, the first insulation layer is etched and the substrate is also continued to be etched by using the patterned photoresist as a mask, so as to form a housing space, wherein a depth of the housing space is at least two orders greater than a thickness of the first insulation layer. Thereafter, the patterned photoresist is removed, and a second insulation layer is formed on a surface of the substrate.

What is claimed is: 
     
         1 . A method of manufacturing a three-dimensional nanochannel device, comprising:
 forming a first insulation layer on a substrate;   forming a first opening in the first insulation layer;   forming a first patterned photoresist on the first insulation layer, the patterned photoresist comprises at least one second opening, wherein the second opening is adjacent to the first opening and exposes the first insulation layer;   etching the first insulation layer and continuing to etch the substrate by using the patterned photoresist as a mask, so as to form a housing space, wherein a depth of the housing space is at least two orders greater than a thickness of the first insulation layer;   removing the patterned photoresist; and   forming a second insulation layer on an etched surface of the substrate.   
     
     
         2 . The method of manufacturing the three-dimensional nanochannel device as claimed in  claim 1 , wherein the substrate comprises a silicon chip, and the first insulation layer comprises an oxide layer. 
     
     
         3 . The method of manufacturing the three-dimensional nanochannel device as claimed in  claim 1 , wherein a bottom of the housing space is smaller than a top of the housing space. 
     
     
         4 . A method of manufacturing a three-dimensional nanochannel device, comprising:
 etching a silicon chip, so as to form a condensed channel through the silicon chip because different lattice planes in the silicon chip have different etch rates, wherein sizes of the condensed channel on an X-Y plane and sizes of the condensed channel on an X-Z plane are shrunken at least two orders in scale.   
     
     
         5 . The method of manufacturing the three-dimensional nanochannel device as claimed in  claim 4 , wherein the condensed channel is completed by utilizing a single wet etching process.