Circuit And Method For Simultaneously Measuring Multiple Changes In Delay

Abstract

A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits.

What is claimed is: 
     
         1 . An integrated circuit built-in self-test (BIST) circuit, comprising:
 means for measuring a change in delay for rising edges and a change in delay for falling edges;   means for subtracting the change in delay for rising edges from the change in delay for falling edges, to produce a rise-fall mismatch count;   means to comparing the mismatch count to a test limit to produce a pass/fail result.   
     
     
         2 . An integrated circuit built-in self-test (BIST) circuit, comprising:
 means for measuring changes in delays for a plurality of paths in the circuit;   means to subtracting each of the changes in delay from the average of the changes in delay for the plurality of paths, to produce delay-average mismatch counts;   means to comparing each of the mismatch counts to a test limit to produce a pass/fail result.