Semiconductor device having hierarchically structured bit lines and system including the same

Abstract

A device includes first memory blocks each including a first local bit line, first memory cells connected to the first local bit line and a first hierarchy switch connected between a first global bit line and the first local bit line, a dummy global bit line connected to the second node of a first sense amplifier, a dummy block including a dummy local bit line, dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line, and a control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information.

What is claimed is: 
     
         1 . A device comprising:
 a first sense amplifier including first and second nodes;   a first global bit line connected to the first node of the first sense amplifier;   a plurality of first memory blocks each including a first local bit line, a plurality of first memory cells connected to the first local bit line and a first hierarchy switch connected between the first global bit line and the first local bit line;   a dummy global bit line connected to the second node of the first sense amplifier;   a dummy block including a dummy local bit line, a plurality of dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line; and   a control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information.   
     
     
         2 . The device as claimed in  claim 1 ,
 wherein the device further comprises a second sense amplifier including third and fourth nodes, and a second global bit line connected to the third node of the second sense amplifier,   wherein each of the first memory blocks further includes a second local bit line, a plurality of memory cells connected to the second local bit line and a second hierarchy switch connected between the second global bit line and the second local bit line, and   wherein the control circuit is configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first and second hierarchy switches of one of the first memory blocks designated by the address information.   
     
     
         3 . The device as claimed in  claim 2 ,
 wherein the device further comprises:
 a third global bit line connected to the fourth node of the second sense amplifier; and 
 a plurality of second memory blocks each including a third local bit line, a plurality of third memory cells connected to the third local bit line and a third hierarchy switch connected between the third global bit line and the third local bit line, and 
   wherein the control circuit is configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block, the first and second hierarchy switches of one of the first memory blocks designated by the address information and the third hierarchy switch of one of the second memory blocks.   
     
     
         4 . The device as claimed in  claim 3 , wherein the first memory blocks are arranged in line on a left side of the second sense amplifier; the second memory blocks are arranged in line on a right side of the second sense amplifier; and the one of the first memory blocks designated by the address information and the one of the second memory blocks are symmetrical in position with respect to the second sense amplifier. 
     
     
         5 . The device as claimed in  claim 3 , wherein the control circuit is configured to respond to the address information designating any one of the second memory blocks to turn OFF the dummy hierarchy switch of the dummy block and turn ON each of the third hierarchy switch of one of the second memory blocks designated by the address information and the second hierarchy switch of one of the first memory blocks. 
     
     
         6 . The device as claimed in  claim 5 , wherein the first memory blocks are arranged in line on a left side of the second sense amplifier; the second memory blocks are arranged in line on a right side of the second sense amplifier; and the one of the second memory blocks designated by the address information and the one of the first memory blocks are symmetrical in position with respect to the second sense amplifier. 
     
     
         7 . The device as claimed in  claim 1 ,
 wherein the first memory blocks belong to a first memory mat,   wherein the address information includes a mat address part and a block address part, and   wherein the control circuit includes first and second circuits, the first circuit responding to the mat address part designating the first memory mat to turn ON the dummy hierarchy switch, and the second circuit responding to the mat and block address parts to turn ON the first hierarchy switch of one of the first memory blocks designated by the mat and block address parts.   
     
     
         8 . The device as claimed in  claim 5 ,
 wherein the first memory blocks belong to a first memory mat and the second memory blocks belong to a second memory mat,   wherein the address information includes a mat address part and a block address part, and   wherein the control circuit includes first and second circuits, the first circuit responding to the mat address part designating the first memory mat to turn ON the dummy hierarchy switch and responding to the mat address part designating the second memory mat to turn OFF the dummy hierarchy switch, and the second circuit responding to the mat and block address parts to bring one of first and second states, the first state being such that the first and second hierarchy switches of one of the first memory blocks designated by the mat and block address parts are turned ON, and the second state being such that the third hierarchy switches of one of the second memory blocks designated by the mat and block address parts and the second hierarchy switches of one of the first memory blocks are turned ON.   
     
     
         9 . The device as claimed in  claim 1 , wherein the dummy local bit line and the first local bit lines are substantially equal in length to one another. 
     
     
         10 . A device comprising:
 a plurality of sense amplifier circuits including a first sense amplifier circuit;   a first global bit line;   a dummy global bit line;   a plurality of first memory blocks that are arranged in a first direction, each of the first memory blocks including a first hierarchy switch that is coupled to the first global bit line, a first local bit line that is coupled to the first hierarchy switch, and a memory cell coupled to the first local bit line;   a dummy memory block including a dummy hierarchy switch that is coupled to the dummy global bit line, a dummy local bit line that is coupled to the dummy global bit line via the dummy hierarchy switch, and a dummy memory cell coupled to the dummy local bit line; and   a control circuit including:
 a first control circuit which receives first address information and controls the first hierarchy switches of the first memory blocks, and 
 a second control circuit which receives second address information and controls the dummy hierarchy switch, 
   wherein the first sense amplifier circuit is arranged between the first memory blocks and the dummy memory block, and amplifies a potential difference between the first global bit line and the dummy global bit line, and   wherein the first address information is larger in bit number than the second address information.   
     
     
         11 . The device as claimed in  claim 10 , wherein the memory cell that includes a pillar transistor including a pillar-shaped channel that is substantially perpendicular to a main surface of a semiconductor substrate. 
     
     
         12 . The device as claimed in  claim 11 , wherein each of the memory cell and the dummy memory cell includes a series circuit of a cell transistor and a memory element that stores information therein. 
     
     
         13 . The device as claimed in  claim 12 , wherein the memory element comprises a capacitor. 
     
     
         14 . The device as claimed in  claim 11 , wherein each of the first hierarchy switch and the dummy hierarchy switch comprises a pillar transistor including a pillar-shaped channel that is substantially perpendicular to a main surface of a semiconductor substrate. 
     
     
         15 . The device as claimed in  claim 10 , wherein each of the first hierarchy switch and the dummy hierarchy switch comprises a pillar transistor including a pillar-shaped channel that is substantially perpendicular to a main surface of a semiconductor substrate. 
     
     
         16 . The device as claimed in  claim 10 , wherein the first global bit line is greater in length than the dummy global bit line. 
     
     
         17 . The device as claimed in  claim 10 , wherein a number of the memory cells coupled to the first local bit lines allocated to the first sense amplifier circuit is larger than a number of the dummy memory cells coupled to the dummy local bit line allocated to the first sense amplifier circuit. 
     
     
         18 . The device as claimed in  claim 10 , wherein the first control circuit selects one of the first memory blocks. 
     
     
         19 . The device as claimed in  claim 10 , wherein the first local bit line is substantially equal in length to the dummy local bit line. 
     
     
         20 . The device as claimed in  claim 10 , wherein the first global bit line is greater in length than the dummy global bit line, and the first local bit line is substantially equal in length to the dummy local bit line. 
     
     
         21 . The device as claimed in  claim 10 , wherein the first address information includes the second address information.