Semiconductor switch

Abstract

A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

1 . A level shifting circuit, comprising:
 first and second supply voltages, said first supply voltage being greater than said second supply voltage;   an output terminal;   a high side semiconductor switch connected between said first supply voltage and said output terminal;   a low side semiconductor switch connected between said output terminal and said second supply voltage;   said high side semiconductor switch comprising:   a substrate;   a first PNPN structure on said substrate;   electrical contacts which provide first anode, first gate and first cathode connections to said first PNPN structure;   a first external node; and   a PMOS FET on said substrate arranged to conduct a current between said first external node and said electrical contact which provides said first anode connection when on and to inhibit the current conducted between said first external node and said electrical contact which provides said first anode connection and thereby turn off said high side semiconductor switch when off,   said first PNPN structure arranged to conduct a current between said electrical contact which provides said first anode connection and said electrical contact which provides said first cathode connection when a threshold voltage is applied to said electrical contact which provides said first gate connection to said PNPN structure, and to maintain said current conduction via regenerative feedback as long as said current conducted between said electrical contact which provides said first anode connection and electrical contact which provides said first cathode connection is larger than a threshold current, said first external node coupled to said first supply voltage and said first cathode coupled to said output terminal;   said low side semiconductor switch comprising:   a substrate;   a second PNPN structure on said substrate;   electrical contacts which provide second anode, second gate and second cathode connections to said second PNPN structure;   a second external node; and   a NMOS FET on said substrate arranged to conduct a current between said second external node and said electrical contact which provides said cathode connection when on and to inhibit the current conducted between said second external node and said electrical contact which provides said cathode connection and thereby turn off said low side semiconductor switch when off,   said second external node coupled to said second supply voltage and said second anode coupled to said output terminal,   said second PNPN structure arranged to conduct a current between said electrical contact which provides said second cathode connection and said electrical contact which provides said second anode connection when a threshold voltage is applied to said electrical contact which provides said second gate connection to said PNPN structure, and to maintain said current conduction via regenerative feedback as long as said current conducted between said electrical contact which provides said second anode connection and electrical contact which provides said second cathode connection is larger than a threshold.   
     
     
         2 . The level shifting circuit of  claim 1 ,
 wherein said high side switch PMOS and low side switch NMOS FETs comprise a plurality of source, drain and gate regions which may be interconnected to a controller as needed to provide multiple functions, at least one of said PMOS FET's source, drain and gate regions arranged to form a PMOS FET which, when turned on in response to a first control signal, serves as an active shunt resistance between said first supply voltage and said electrical contact which provides said first PNPN gate connection, and at least one of said NMOS FET's source, drain and gate regions arranged to form a NMOS FET which, when turned on in response to a second control signal, serves as an active shunt resistance between said second supply voltage and said electrical contact which provides said second PNPN gate connection,   said controller further arranged to provide said first and second control signals so as to turn said high side's active shunt resistance on when said high side semiconductor switch is off, and to turn said low side's active shunt resistance on when said low side semiconductor switch is off.   
     
     
         3 . The level shifting circuit of  claim 1 , wherein said PMOS FET is a low voltage p-type MOSFET (LV PMOS) device, and said NMOS FET is a low voltage n-type MOSFET (LV NMOS) device. 
     
     
         4 . The level shifting circuit of  claim 1 ,
 wherein the first PNPN structure includes parallel and adjacent stripe-shaped planar regions formed in a top surface of said substrate, and   wherein the PMOS FET is planar in structure formed in the top surface of the substrate adjacent the first PNPN structure, and comprising parallel and adjacent stripe-shaped source, gate and drain regions,   such that, when the top surface of said substrate is viewed from above in a plan view, said first PNPN structure's parallel and adjacent stripe-shaped planar regions are oriented such that they are parallel to a first axis of the PMOS FET oriented such that said PMOS FET first axis, parallel and adjacent stripe-shaped source, gate and drain planar regions lie perpendicular to said first axis, such that said first PNPN structure and said PMOS FET structure can be sized independently; and   wherein the second PNPN structure includes parallel and adjacent stripe-shaped planar religions formed in the top surface of said substrate, and   wherein the NMOS FET is planar in structure formed in the top surface of the substrate adjacent the second PNPN structure, and comprising parallel and adjacent stripe-shaped source, gate and drain regions,   such that, when the top surface of said substrate is viewed from above in a plan view, said second PNPN structure's parallel and adjacent stripe-shaped planar regions are oriented such that they are parallel to a first axis of the NMOS FET is oriented such that said NMOS FET first axis, parallel and adjacent stripe-shaped source, gate and drain planar regions lie perpendicular to said first axis, such that said second PNPN structure and said PMOS FET structure can be sized independently.   
     
     
         5 . The level shifting circuit of  claim 1  further including:
 a controller arranged to provide control signals to said electrical contacts which provide said connections to said first and second gate connections to said first and second PNPN structures and said MOSFETs such that said high side and low side semiconductor switches are alternately turned on and off as needed to toggle the voltage at said output terminal back and forth between a voltage approximately equal to said first supply voltage and a voltage approximately equal to said second supply voltage. 
 
     
     
         6 . A level shifting circuit, comprising:
 first and second supply voltages, said first supply voltage being greater than said second supply voltage;   an output terminal;   a high side semiconductor switch connected between said first supply voltage and said output terminal;   a low side semiconductor switch connected between said output terminal and said second supply voltage;   said high side semiconductor switch comprising:   a substrate having top and bottom surfaces;   a first p type planar source region and first p type planar drain region formed adjacent to each other in the top surface of said substrate;   a first n type planar region formed laterally adjacent to said first p type drain region in the top surface of said substrate;   a second p-type planar region formed laterally adjacent to said first n type region on said substrate, said first p type planar regions and second p-type region and said first n type region arranged to form a first effective PNP transistor;   a second n-type region formed laterally adjacent to said second p-type region on said substrate, said first and second n-type regions and said second p-type region arranged to form a first effective NPN transistor, said first effective PNP and first effective NPN transistors arranged to form a first PNPN silicon-controlled first rectifier (SCR) structure;   an electrical contact on said first p type planar drain region to provide a first anode for said first SCR structure;   an electrical contact on said first n type planar region to provide a gate for said first SCR structure;   an electrical contact on said second n type planar region to provide a first cathode for said first SCR structure;   a first external node; and   a PMOS FET formed in the top surface of said substrate, including the first p type planar source region and first p type planar drain region, arranged to conduct a current between said first external node and said first anode when on and to inhibit the current conducted between said first external node and said first anode and when off,   said first PNPN structure arranged to conduct a current between said first external node and said first cathode when a voltage greater than a threshold voltage is applied to said electrical contact which provides said gate, and to maintain said current conduction via regenerative feedback when the voltage applied to said electrical contact which provides said gate falls below said threshold voltage as long as said current conducted between said first external node and said first cathode is greater than a threshold current;   wherein the first supply voltage is coupled to the first external node and the first cathode node is coupled to the output terminal;   said low side semiconductor switch comprising:   a first n type planar source region and first n type planar drain region formed adjacent to each other in the top surface of said substrate;   a first p type planar region formed laterally adjacent to said first n type drain region in the top surface of said substrate;   a second n-type planar region formed laterally adjacent to said first p type region on said substrate, said first n type planar regions and second n type region and said first p type region arranged to form a second effective NPN transistor;   a second p-type region formed laterally adjacent to said second n-type region on said substrate, said first and second p-type regions and said second n-type region arranged to form a second PNP transistor, said second effective NPN and PNP transistors arranged to form a second PNPN silicon-controlled rectifier (SCR) structure;   an electrical contact on said first n type planar drain region to provide a second cathode node for said second SCR structure;   an electrical contact on said first p-type planar region to provide a gate for said second SCR structure;   an electrical contact on said second p-type planar region to provide a second anode for said second SCR structure;   a second external node; and   an NMOS FET formed in the top surface of said substrate, including the first n type planar source region and first n type planar drain region, arranged to conduct a current between said second external node and said second cathode when on and to inhibit the current between said second external node and said second cathode for said when off,   said second PNPN structure arranged to conduct a current between said second anode and said second external node when a voltage beyond a threshold voltage is applied to said electrical contact which provides said gate for said second SCR structure, and to maintain said current conduction via regenerative feedback when the voltage applied to said electrical contact which provides said gate for said second SCR structure falls below said threshold voltage as long as said current conducted between said anode and second external node is greater than a threshold current   wherein the second supply voltage is coupled to the second external node and the second anode is coupled to the output terminal.   
     
     
         7 . The level shifting circuit of  claim 6  comprising,
 a high side semiconductor switch, 
 wherein said first n type, second p type, and second n type planar regions are parallel, stripe-shaped planar regions which form the first PNPN structure with said first p-type planar regions, and said PMOS FET is a planar structure comprising parallel and adjacent stripe-shaped source, gate and drain planar regions formed in the top surface of said substrate adjacent to said first PNPN structure, 
 such that when the top surface of said substrate is viewed from above in a plan view, said first PNPN structure's parallel stripe-shaped planar regions are oriented such that they are parallel to a first axis and said PMOS FET is oriented such that said PMOS FET's parallel and adjacent stripe-shaped source, gate and drain planar regions lie perpendicular to said first axis, such that said first PNPN structure and said PMOS FET structure can be sized independently; and 
 
       a low side semiconductor switch,
 wherein said first p type, second n type and second p-type planar regions are parallel, stripe-shaped planar regions which form the second PNPN structure with said first n type planar regions, and said NMOS FET is a planar structure comprising parallel and adjacent stripe-shaped source, gate and drain planar regions formed in the top surface of said substrate adjacent to said second PNPN structure, 
 such that when the top surface of said substrate is viewed from above in a plan view, said second PNPN structure's parallel stripe-shaped planar regions are oriented such that they are parallel to a first axis and said NMOS FET is oriented such that the NMOS FET's parallel and adjacent stripe-shaped source, gate and drain planar regions lie perpendicular to said first axis, such that said second PNPN structure and said NMOS FET structure can be sized independently. 
 
     
     
         8 . The level shifting circuit of  claim 7 ,
 wherein said PMOS FET comprises: a plurality of pairs of heavily-doped stripe-shaped p-type regions oriented perpendicularly to said first axis, one heavily-doped stripe-shaped p-type region of each pair being a drain region and the other heavily-doped stripe-shaped p-type region of each pair being a source region, the heavily-doped stripe-shaped p-type regions of each pair located on opposite sides of a respective one of said stripe-shaped gate regions, wherein at least one source, drain and gate region are arranged to form said PMOS FET which conducts a current between said first external node and said anode when on and inhibits the flow of-current conducted between said first external node and said first anode and thereby turns off said high-side semiconductor switch when off, the drain regions and source regions of said PMOS FET comprising said first anode and said first external node, respectively; and   wherein said NMOS FET comprises: a plurality of pairs of stripe-shaped n-type regions oriented perpendicularly to said first axis, one stripe-shaped n-type region of each pair being a drain region and the other stripe-shaped n-type region of each pair being a source region, the stripe-shaped n-type regions of each pair located on opposite sides of a respective one of said stripe-shaped gate regions, wherein at least one source, drain and gate region are arranged to form said NMOS FET which conducts a current between said second external node and said cathode when on and inhibits the current conducted between said second external node and said second cathode and thereby turns off said low-side semiconductor switch when off, the drain regions and source regions of said NMOS FET comprising said second cathode and said second external node, respectively.   
     
     
         9 . The level shifting circuit of  claim 8 ,
 wherein at least one source, drain and gate region are arranged to form a second PMOS FET in the high side semiconductor switch which, when on, serves as a shunt resistor between said first external node and said first PNPN structure's gate electrical contact; and   wherein at least one source, drain and gate region are arranged to form a second NMOS FET in the low side semiconductor switch which, when on, serves as a shunt resistor between said second external node and said second PNPN structure's gate electrical contact.   
     
     
         10 . The level shifting circuit of  claim 8 ,
 wherein each of said first anode regions in the high side semiconductor switch further comprises a first contiguous heavily-doped stripe-shaped p-type region oriented parallel to said first axis when the top surface of said substrate is viewed from above in a plan view, such that said anode regions provide a larger interface area with said first n type planar region than do said first external nodes; and   wherein each of said second cathode regions in the low side semiconductor switch further comprises a first contiguous heavily-doped stripe-shaped n-type region oriented parallel to said first axis when the top surface of said substrate is viewed from above in a plan view such that said cathode regions provide a larger interface area with said first p type planar region than do said second external nodes.   
     
     
         11 . The level shifting circuit of  claim 10 ,
 wherein said first n type planar region comprises an n+ portion immediately adjacent to said PMOSFET,   said external nodes arranged to terminate at said n+ portion immediately adjacent to said PMOS FET so as to depress the beta value of transistor formed by said external nodes, said first n type stripe-shaped planar region, and said stripe-shaped p type planar anode region; and   wherein said first p type stripe-shaped planar region comprises a p+ portion immediately adjacent to said NMOS FET,   said external nodes arranged to terminate at said p+ portion immediately adjacent to said NMOS FET so as to depress the beta value of transistor formed by said external nodes, said first p-type stripe-shaped planar region, and said stripe-shaped n type planar cathode region.   
     
     
         12 . The level shifting circuit of  claim 10 ,
 wherein said PMOS FET is arranged as a symmetrical device and further comprising another PNPN structure comprising parallel and adjacent stripe shaped planar regions formed in the top surface of said substrate and oriented such that they are parallel to said first axis when the top surface of said substrate is viewed from above in a plan view, said another PNPN structure located adjacent to said PMOS FET on the opposite side of said PMOS FET from said first PNPN structure, such that said semiconductor switch is symmetrical,   wherein each of said anodes further comprises a second contiguous stripe-shaped p-type region oriented parallel to said first axis when the top surface of said substrate is viewed from above in a plan view, each of said anodes being I-shaped with said first and second contiguous stripe-shaped p-type regions being at opposite ends of said anodes stripe-shaped p-type planar region oriented perpendicularly to said first axis, such that said first and second contiguous regions serve as an anode for said first PNPN structure and said another PNPN structure, respectively:   wherein said NMOS FET is arranged as a symmetrical device and further comprising still another PNPN structure comprising parallel and adjacent stripe shaped planar regions formed in the top surface of said substrate and oriented such that they are parallel to said first axis when the top surface of said substrate is viewed from above in a plan view, said another PNPN structure located adjacent to said NMOS FET on the opposite side of said NMOS FET from said first PNPN structure, such that said semiconductor switch is symmetrical,   wherein each of said cathodes further comprises a second contiguous stripe-shaped n-type region oriented parallel to said first axis when the top surface of said substrate is viewed from above in a plan view, each of said cathodes being I-shaped with said first and second contiguous stripe-shaped n-type regions being at opposite ends of said cathodes stripe-shaped n-type planar region oriented perpendicularly to said first axis, such that said first and second contiguous regions serve as an cathode for said first PNPN structure and said another PNPN structure, respectively.   
     
     
         13 . The level shifting circuit of  claim 6 ,
 wherein said PMOS FET is arranged such that its channel resistance serves as a ballast resistor which limits the current conducted between said first external node and said first anode; and   wherein said NMOS FET is arranged such that its channel resistance serves as a ballast resistor which limits the current conducted between said second external node and said second cathode.   
     
     
         14 . The level shifting circuit of  claim 6 , further comprising:
 a third p-type region in the high side semiconductor switch formed laterally adjacent to and electrically connected to said second n-type region, said third p-type region and said second p-type planar region having resistance between them which serves as a shunt resistor between said first cathode and the base of said first effective NPN transistor; and   a third n-type region in the low side semiconductor switch formed laterally adjacent to and electrically connected to said second p-type region, said third n-type region and said second n-type planar region having resistance between them which serves the—as shunt resistor between said second anode and the base of said second effective PNP transistor.   
     
     
         15 . The level shifting circuit of  claim 6 ,
 wherein said second n-type planar region serves as an emitter for said first NPN transistor; and   wherein said second p-type planar region serves as an emitter for said second PNP transistor.   
     
     
         16 . The level shifting circuit of  claim 6 ,
 wherein the low side semiconductor switch: said first p type planar region is a p+ region;   said first n type planar region is an n-well (NW) region;   said second p type planar region is a p-well (PW) region; and   said second n type region is a n+ region; and   wherein the high side semiconductor switch: said first n-type planar region is a n+ region;   said first p type planar region is an p-well (NW) region;   said second n type planar region is a n-well (PW) region; and   said second p type region is a p+ region.   
     
     
         17 . The level shifting circuit of  claim 6 , further comprising:
 a p-well (PW) region which encloses said second p type planar region and said second n-type region such that a blocking junction is formed between said PW region and said first n type planar region; and   an n-well (NW) region which encloses said second n type planar region and said second p-type region such that a blocking junction is formed between said NW region and said first p type planar region.   
     
     
         18 . The level shifting circuit of  claim 6 , further comprising:
 a n type buried layer (NBL) located such that it electrically isolates said low side switch from said substrate; and   a n type buried layer (NBL) located such that it electrically isolates said low side switch from said substrate.   
     
     
         19 . The level shifting circuit of  claim 6 , further comprising:
 a third p type region formed laterally adjacent to and electrically connected to said second n type region; and a third n-type region formed laterally adjacent to said third p-type region and electrically connected to said first n type region; and   a third n type region formed laterally adjacent to and electrically connected to said second p-type region; and a third p type region formed laterally adjacent to said third n type region and electrically connected to said first p type region.   
     
     
         20 . The level shifting circuit of  claim 19 ,
 wherein said third p-type f region and said third n-type region form a diode which provides a reverse conduction path through said semiconductor switch which acts to discharge high stress EOS/ESD current conducted between said cathode and said first external node of said high-side semiconductor switch; and   wherein said third n-type planar region and said third p-type region form a diode which provides a reverse conduction path through said semiconductor switch which acts to discharge high stress EOS/ESD current conducted between said second external node and said anode of said low-side semiconductor switch.