Via Structure for Multi-Gigahertz Signaling

Abstract

A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.

What is claimed is: 
     
         1 . A multi-layer printed circuit board (PCB), comprising:
 a first capacitor formed by a first closed geometric structure formed onto a surface of a substrate and a second closed geometric structure formed onto the surface of the substrate to enclose the first closed geometric structure, wherein the second closed geometric structure is electrically isolated from the first closed geometric structure; and   a second capacitor formed by the first closed geometric structure and a third closed geometric structure formed onto the surface of the substrate, wherein the third closed geometric structure is formed around the second closed geometric structure, and wherein the third closed geometric structure is electrically isolated from the first closed geometric structure and the second closed geometric structure.   
     
     
         2 . The multi-layer PCB of  claim 1 , wherein the first capacitor and the second capacitor are arranged in series. 
     
     
         3 . The multi-layer PCB of  claim 1 , further comprising:
 a first conductive pathway formed onto a second substrate;   a second conductive pathway formed onto a third substrate; and   a connecting structure formed through the substrate to connect the first conductive pathway to the second conductive pathway.   
     
     
         4 . The multi-layer PCB of  claim 3 , wherein the substrate is positioned between the second substrate and the third substrate. 
     
     
         5 . The multi-layer PCB of  claim 1 , wherein the first closed geometric structure and the second closed geometric structure comprise regular polygons. 
     
     
         6 . The multi-layer PCB of  claim 1 , wherein the first closed geometric structure and the second closed geometric structure comprise regular circular rings. 
     
     
         7 . The multi-layer PCB of  claim 1 , wherein the wherein the first closed geometric structure and the second dosed geometric structure comprise concentric circular rings. 
     
     
         8 . The multi-layer PCB of  claim 1 , wherein the second dosed geometric structure is characterized by a first width and a first thickness, wherein the first width represents a first region from the first closed geometric structure in the substrate that is free of conductive material, and wherein the first thickness represents a thickness of the second closed geometric structure. 
     
     
         9 . A multi-layer printed circuit board (PCB), comprising:
 a first closed geometric structure formed onto a surface of a substrate; and   a second closed geometric structure formed onto the surface of the substrate to enclose the first closed geometric structure, wherein the second closed geometric structure is electrically isolated from the first closed geometric structure, wherein the second closed geometric structure is characterized by a first width and a first thickness, wherein the first width represents a first region from the first dosed geometric structure in the substrate that is free of conductive material, and wherein the first thickness represents a thickness of the second dosed geometric structure.   
     
     
         10 . The multi-layer PCB of  claim 9 , wherein the first closed geometric structure and the second closed geometric structure form a capacitor. 
     
     
         11 . The multi-layer PCB of  claim 9 , further comprising:
 a third closed geometric structure formed onto the surface of the substrate to enclose the second closed geometric structure.   
     
     
         12 . The multi-layer PCB of  claim 11 , wherein the second closed geometric structure and the third closed geometric structure form a capacitor. 
     
     
         13 . The multi-layer PCB of  claim 9 , wherein the first closed geometric structure comprises:
 a regular polygon.   
     
     
         14 . The multi-layer PCB of  claim 9 , wherein the first closed geometric structure comprises:
 a circular ring.   
     
     
         15 . The multi-layer PCB of  claim 9 ,
 wherein the first closed geometric structure is characterized by a second width and a second thickness,   wherein the second width represents a second region in the substrate that is free of conductive material, and   wherein the second thickness represents a thickness of the first closed geometric structure.   
     
     
         16 . The multi-layer PCB of  claim 15 , wherein the second width and the second thickness represent design parameters to be used by electronic design automation (EDA) software. 
     
     
         17 . A multi-layer printed circuit board (PCB), comprising:
 a first closed geometric structure formed onto a surface of a substrate;   a second closed geometric structure formed onto the surface of the substrate to enclose the first closed geometric structure, wherein the second closed geometric structure is electrically isolated from the first closed geometric structure; and   a third closed geometric structure formed onto the surface of the substrate, wherein the third closed geometric structure is formed around the second closed geometric structure, and wherein the third closed geometric structure is electrically isolated from the first closed geometric structure and the second closed geometric structure.   
     
     
         18 . The multi-layer PCB of  claim 17 , wherein the first closed geometric structure and the second closed geometric structure form a first capacitor, and wherein the second closed geometric structure and the third closed geometric structure form a second capacitor. 
     
     
         19 . The multi-layer PCB of  claim 17 , further comprising:
 a first conductive pathway formed onto a second substrate;   a second conductive pathway formed onto a third substrate; and   a connecting structure formed through the substrate to connect the first conductive pathway to the second conductive pathway.   
     
     
         20 . The multi-layer PCB of  claim 17 ,
 wherein the first closed geometric structure is characterized by a width and a thickness,   wherein the width represents a region in the substrate that is free of conductive material, and   wherein the thickness represents a thickness of the first closed geometric structure.