Oscillator settling time allowance

Abstract

Techniques are disclosed relating to oscillator settling time allowance. In one embodiment, an apparatus may include an oscillator and oscillation detection and control circuitry. The oscillation detection and control circuitry may be configured to awaken an oscillator at a predetermined time and detect an edge transition of oscillations. The oscillation detection and control circuitry may further be configured to measure the time from the power-on indication to edge transition detection. In one embodiment, the oscillation detection and control circuitry may be configured to store the measured time and use the measured time instead of the predetermined time for subsequent oscillator awakenings. In some embodiments, the apparatus may further include circuitry configured to compensate for an expected oscillator settling behavior.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a crystal oscillator configured to awake from a sleep mode at a time based on a clock from a low power oscillator, wherein the crystal oscillator is further configured to oscillate at an output frequency;   logic configured to apply digital compensation to an oscillation of the crystal oscillator; and   a receiver configured to receive the digitally compensated oscillation from the logic and to activate before the crystal oscillator settles within a predetermined tolerance.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 additional logic configured to apply digital modification to an oscillation of the crystal oscillator; and   a transmitter configured to receive the digitally modified oscillation and to activate before the crystal oscillator settles within a predetermined tolerance.   
     
     
         3 . The apparatus of  claim 1 , wherein the digital compensation includes an exponentially-shaped frequency ramp. 
     
     
         4 . The apparatus of  claim 1 , wherein the digital compensation includes an interpolation.