System on chip, method of operating the same, and devices including the system on chip

Abstract

A method of operating a system on chip (SoC) includes converting plain data into cipher data by using an encryption key and transmitting the cipher data directly to a memory controller which controls an operation of a non-volatile memory. The encryption key may be output by a one-time programmable (OTP) memory.

What is claimed is: 
     
         1 . A method of operating a system on chip (SoC), the method comprising:
 converting plain data into cipher data by an engine within the SoC using a encryption key; and   transmitting, by the engine, the cipher data directly to a memory controller within the SoC,   wherein the memory controller controls an operation of a non-volatile memory.   
     
     
         2 . The method of  claim 1 , wherein prior to the converting, the method comprises the SoC reading the plain data from a main memory via a bus under the control of a central processing unit (CPU). 
     
     
         3 . The method of  claim 1 , wherein prior to the converting, the method comprises a direct memory access (DMA) unit within the SoC outputting the plain data to the engine. 
     
     
         4 . The method of  claim 1 , wherein prior to the converting, the method comprises a one-time programmable (OTP) memory within the SoC outputting the encryption key to the engine. 
     
     
         5 . The method of  claim 1 , wherein prior to the converting, the method comprising outputting the encryption key to the engine only while a secure program is being executed. 
     
     
         6 . The method of  claim 1 , wherein the converting comprises converting the plain data into the cipher data in units of blocks. 
     
     
         7 . A method of operating a system on chip (SoC), the method comprising:
 receiving, by an engine within the SoC, cipher data directly from a memory controller within the SoC, wherein the memory controller controls an operation of a non-volatile memory; and   converting, by the engine, the cipher data into plain data using a encryption key.   
     
     
         8 . The method of  claim 7 , wherein prior to the converting, the method comprises transmitting the plain data from a direct memory access (DMA) unit within the SoC to the engine. 
     
     
         9 . The method of  claim 7 , wherein prior to the converting, the method comprises a one-time programmable (OTP) memory within the SoC outputting the encryption key to the engine. 
     
     
         10 . The method of  claim 7 , wherein prior to the converting, the method comprises outputting the encryption key to the engine only while a secure program is being executed. 
     
     
         11 . The method of  claim 7 , wherein the converting comprises converting the cipher data into the plain data in units of blocks. 
     
     
         12 . A system on chip (SoC) comprising:
 an encryption/decryption engine which encrypts first plain data into first cipher data or decrypts second cipher data into second plain data, using a encryption key; and   a memory controller directly connected to the encryption/decryption engine, wherein the memory controller transmits the first cipher data to a non-volatile memory or receives the second cipher data from the non-volatile memory.   
     
     
         13 . The SoC of  claim 12 , further comprising a one-time programmable (OTP) memory which stores the encryption key. 
     
     
         14 . The SoC of  claim 12 , further comprising a direct memory access (DMA) unit that receives the first plain data from a device outside the SOC and transmits the first plain data to the encryption/decryption engine or transmits the second plain data received from the encryption/decryption engine to the device. 
     
     
         15 . The SoC of  claim 14 , wherein the DMA unit is directly connected to the encryption/decryption engine. 
     
     
         16 . The SoC of  claim 12 , further comprising a central processing unit CPU which controls transmission of the first plain data or the second plain data between a device outside the SoC and the encryption/decryption engine. 
     
     
         17 . A system-in package comprising:
 the SoC of  claim 12 ; and   a device which communicates data with the non-volatile memory under the control of the SoC.   
     
     
         18 . A system-in package comprising:
 the SoC of  claim 12 ;   the non-volatile memory; and   a device which communicates data with the non-volatile memory under the control of the SoC.   
     
     
         19 . A system on chip (SoC) comprises:
 a memory controller configured to control a non-volatile memory; and   an encryption/decryption engine directly connected to the memory controller and configured to encrypt or decrypt data,   wherein the SoC controls transmission of data between a device outside the SoC and the non-volatile memory, and   wherein the memory controller and the engine correspond to a first data path for transmitting data.   
     
     
         20 . The SoC of  claim 19 , wherein the SoC comprises a one-time programmable (OTP) memory storing a key, and the encryption/decryption engine encrypts or decrypts the data by using the key stored in the (OTP) memory. 
     
     
         21 . The SoC of  claim 19 , wherein the first data path further comprises a direct memory access (DMA) unit which receives data from the device and transmits the data to the encryption/decryption engine or receives data from the encryption/decryption engine and transmits the data to the device. 
     
     
         22 . The SoC of  claim 21 , wherein the DMA unit is directly connected to the encryption/decryption engine. 
     
     
         23 . The SoC of  claim 22 , further comprising a second data path which transmits the data which has not been encrypted. 
     
     
         24 . The SoC of  claim 23 , further comprising a selection circuit which selects either the first data path or the second data path based on a selection signal. 
     
     
         25 . The SoC of  claim 24 , further comprising a selection signal generator which generates the selection signal,
 wherein the selection signal generator is an one-time programmable (OTP) memory or a register.   
     
     
         26 . A system on chip (SoC) comprising:
 a data bus;   a main memory controller configured to output plain data to the bus;   an engine configured to encrypt the plain data from the bus into cipher data using a key;   a non-volatile memory (NVM) controller;   a first electrical path connecting the bus to the NVM controller to bypass the encryption engine; and   a second electrical path connecting the bus to the NVM controller through the encryption engine,   wherein the SoC activates only the first electrical path in a non-secure mode for sending the plain data from the bus to the NVM controller, and   wherein the SOC activates only the second electrical path in a secure mode for sending the plain data to the engine and the cipher data from the engine to the NVM controller.   
     
     
         27 . The SoC of  claim 26 , wherein the first electrical path comprises a path of the plain data through a multiplexer and a demultiplexer to the NVM controller. 
     
     
         28 . The SoC of  claim 27 , wherein the second electrical path comprises a path of the plain data through the multiplexer to the engine and a path of the cipher data through the demultiplexer to the NVM controller. 
     
     
         29 . The SoC of  claim 28 , further comprising a one-time programmable (OTP) configured to provide a same selection signal to the multiplexer and the demultiplexer for activating one of the first and the second electrical paths. 
     
     
         30 . The SoC of  claim 26 , wherein the engine is configured to decrypt cipher data received from the NVM controller across the second electrical path.