Multi-level cell memory devices and methods of storing data in and reading data from the memory devices

Abstract

A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

1 . A multi-level cell (MLC) memory device, comprising:
 ‘a’ number of m-bit MLC memory cells;   an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and   a signal mapping module that applies pulses, according to the encoded bit stream, to the ‘a’ number of m-bit MLC memory cells in order to write the encoded bit stream in the ‘a’ number of m-bit MLC memory cells;   wherein ‘a’ and ‘m’ are integers greater than or equal to 2,   wherein ‘k’ and ‘n’ are integers greater than or equal to 1, and   wherein ‘n’ is greater than ‘k’.   
     
     
         2 . The device of  claim 1 , wherein n=a*m. 
     
     
         3 . The device of  claim 1 , wherein n=k+1. 
     
     
         4 . The device of  claim 1 , wherein the encoder comprises:
 an outer encoder that encodes the ‘k’ bits of data at a code rate of k/(k+r 1 ) to generate an outer encoded bit stream; and   an inner encoder that encodes the outer encoded bit stream at a code rate of (k+r 1 )/n to generate the encoded bit stream.   
     
     
         5 . The device of  claim 4 , wherein the outer encoder uses linear block code encoding, and
 wherein the inner encoder uses convolutional code encoding.   
     
     
         6 . The device of  claim 1 , wherein the signal mapping module applies each of the pulses, that are determined for each of the ‘a’ number of m-bit MLC memory cells according to the encoded bit stream, to each of the ‘a’ number of m-bit MLC memory cells. 
     
     
         7 . The device of  claim 6 , wherein each of the pulses is one of 2 m  levels that can be generated by 2 m  pulse amplitude modulation. 
     
     
         8 . The device of  claim 1 , wherein the encoder and the signal mapping module are combined with each other. 
     
     
         9 . The device of  claim 1 , further comprising:
 a signal demapping module;   wherein the signal demapping module generates a demapped bit stream from pulses output from each of the ‘a’ number of m-bit MLC memory cells in response to a read signal.   
     
     
         10 . The device of  claim 9 , wherein the signal demapping module determines partial bit streams demapped from each of the pulses output from each of the ‘a’ number of m-bit MLC memory cells in response to the read signal, and
 wherein the signal demapping module combines the demapped partial bit streams to generate the demapped bit stream. 
 
     
     
         11 . The device of  claim 10 , wherein the signal demapping module compares threshold voltages of 2 m  distributions of each of the ‘a’ number of m-bit MLC memory cells with each of the output pulses to generate the demapped partial bit streams corresponding to each of the output pulses. 
     
     
         12 . The device of  claim 9 , further comprising:
 a decoder;   wherein the decoder decodes the demapped bit stream to generate a decoded bit stream of ‘k’ bits.   
     
     
         13 . The device of  claim 12 , wherein the decoder decodes the demapped bit stream using Viterbi decoding to generate the decoded bit stream. 
     
     
         14 . The device of  claim 12 , wherein the decoder comprises:
 an inner decoder that corrects errors detected from the demapped bit stream to generate an inner decoded bit stream; and   an outer decoder that corrects errors detected from the inner decoded bit stream to generate the decoded bit stream.   
     
     
         15 . The device of  claim 1 , wherein each of the ‘a’ number of m-bit MLC memory cells are memory cells of a MLC flash memory. 
     
     
         16 . A method of storing data in a multi-level cell (MLC) memory device, the method comprising:
 encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and   applying pulses, according to the encoded bit stream, to ‘a’ number of m-bit MLC memory cells in order to write the encoded bit stream in the ‘a’ number of m-bit MLC memory cells;   wherein ‘a’ and ‘m’ are integers greater than or equal to 2,   wherein ‘k’ and ‘n’ are integers greater than or equal to 1, and   wherein ‘n’ is greater than ‘k’.   
     
     
         17 . The method of  claim 16 , wherein n=a*m. 
     
     
         18 . The method of  claim 16 , wherein n=k+1. 
     
     
         19 . A method of reading data from a multi-level cell (MLC) memory device, the method comprising:
 generating a demapped bit stream from pulses output from each of ‘a’ number of m-bit MLC memory cells in response to a read signal; and   decoding ‘n’ bits of data from the demapped bit stream at a code rate of n/k to generate a decoded bit stream;   wherein ‘a’ and ‘m’ are integers greater than or equal to 2,   wherein ‘k’ and ‘n’ are integers greater than or equal to 1, and   wherein ‘n’ is greater than ‘k’.   
     
     
         20 . The method of  claim 19 , wherein n=a*m. 
     
     
         21 . (canceled)