Control driven synchronous rectifier scheme for isolated active clamp forward power converters

Abstract

A synchronous rectification circuit includes a transformer receiving an input voltage at a primary side and outputting an output voltage at a secondary side and a controller arranged and programmed to operate independently from the input and output voltages. The controller preferably outputs control signals to switching logic devices, the switching logic devices being arranged to output timing signals to drive individual synchronous rectifiers included in the secondary side of the transformer. The synchronous rectification circuit includes at least one logic gate which receives the control signals output from the controller and supplies clock signals to the switching logic devices, the clock signals being generated by the at least one logic gate based on the control signal and driving devices arranged to receive the timing signals from a respective one of the switching logic devices, the driving devices driving the synchronous rectifiers in accordance with the timing signals.

What is claimed is: 
     
         1 . A synchronous rectification circuit, comprising:
 a transformer arranged to receive an input voltage at a primary side and output an output voltage at a secondary side;   a controller arranged and programmed to operate independently from the input voltage and the output voltage, the controller arranged to output control signals;   at least two switching logic devices each being arranged to output timing signals used to drive individual ones of at least two synchronous rectifiers included in the secondary side of the transformer;   at least one logic gate arranged to receive the control signals output from the controller and to supply clock signals to the at least two switching logic devices, the clock signals being generated by the at least one logic gate based on the control signals; and   at least two driving devices arranged to receive the timing signals from a respective one of the at least switching logic devices, the at least two driving devices being arranged to drive the individual ones of the at least two synchronous rectifiers in accordance with the timing signals.   
     
     
         2 . The synchronous rectification circuit according to  claim 1 , wherein each of the at least two driving devices are arranged to receive timing signals from a same one of the at least two switching logic devices. 
     
     
         3 . The synchronous rectification circuit according to  claim 2 , wherein one of the at least two driving devices is arranged to receive one of the control signals output from the controller. 
     
     
         4 . The synchronous rectification circuit according to  claim 1 , further comprising a digital isolator arranged between the controller and the two at least switching logic devices, the at least one logic gate, and the at least two driving devices; wherein the digital isolator is arranged to receive the control signals from the controller and then to output the control signals. 
     
     
         5 . The synchronous rectification circuit according to  claim 1 , wherein the control signals include a first control signal and a second control signal, the at least one logic gate being arranged to generate one of the clock signals based on the first control signal and the second control signal. 
     
     
         6 . The synchronous rectification circuit according to  claim 5 , wherein the at least one logic gate is arranged to generate the one of the clock signals such that:
 on a first pulse of the one of the clock signals, a rising edge of the first control signal corresponds to a rising edge of the one of the clock signals and a rising edge of the second control signal corresponds to a falling edge of the one of the clock signals; and   on a next clock pulse of the one of the clock signals, falling edges of the first control signal and the second control signal correspond to the next clock pulse.   
     
     
         7 . The synchronous rectification circuit according to  claim 5 , wherein the first control signal is a clamp signal and the second control signal is a primary switching signal. 
     
     
         8 . The synchronous rectification circuit according to  claim 6 , wherein one of the at least two switching logic devices is arranged to generate a freewheeling signal based on the one of the clock signals, the freewheeling signal being input into one of the at least two driving devices. 
     
     
         9 . The synchronous rectification circuit according to  claim 8 , wherein the one of the at least two switching logic devices is arranged to generate the freewheeling signal based on one of the first control signal and the second control signal and also based on signals output from the at least one logic gate. 
     
     
         10 . The synchronous rectification circuit according to  claim 2 , wherein the timing signals received by each of the at least two driving devices from the same one of the at least switching logic devices are delayed. 
     
     
         11 . The synchronous rectification circuit according to  claim 10 , wherein the delay in the timing signals is caused by a resistor and a capacitor connected to an output of the same one of the at least two switching logic devices. 
     
     
         12 . The synchronous rectification circuit according to  claim 8 , wherein the freewheeling signal supplied to the one of the at least two driving devices is delayed. 
     
     
         13 . The synchronous rectification circuit according to  claim 12 , wherein the delay in the freewheeling signal is caused by a resistor, a diode, and a capacitor connected to an output of the same one of the at least two switching logic devices. 
     
     
         14 . The synchronous rectification circuit according to  claim 1 , further comprising a start up regulator arranged to supply power to the controller. 
     
     
         15 . The synchronous rectification circuit according to  claim 1 , wherein the at least two switching logic devices are flip-flops. 
     
     
         16 . The synchronous rectification circuit according to  claim 1 , wherein the at least one logic gate includes an exclusive OR gate. 
     
     
         17 . The synchronous rectification circuit according to  claim 1 , wherein the at least two driving devices are MOSFET drivers. 
     
     
         18 . The synchronous rectification circuit according to  claim 1 , wherein the synchronous rectification circuit is arranged to define an active clamp forward converter.