Method and Apparatus for Reading a Programmable Anti-Fuse Element in a High-Voltage Integrated Circuit

Abstract

A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

1 - 14 . (canceled) 
     
     
         15 . A method for reading a programmable anti-fuse block of a power integrated circuit (IC) comprising:
 providing a first voltage at a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state;   generating a read signal that turns on a plurality of selector switches, each selector switch being coupled to a corresponding one of the anti-fuses; and   latching a voltage potential at a second node of each selector switch, the voltage potential being representative of the programmed state of each anti-fuse.   
     
     
         16 . The method of  claim 15  further comprising reading the latched programmed state of each anti-fuse by a controller of the power IC. 
     
     
         17 . The method of  claim 15  further comprising decoupling the programmable anti-fuse block from the first node. 
     
     
         18 . The method of  claim 15  wherein each selector switch comprises a field-effect transistor (FET) having a drain coupled to a corresponding one of the anti-fuses, each selector switch also having a gate and a source. 
     
     
         19 . The method of  claim 15  further comprising applying an external voltage to a pin of the power IC, the pin being coupled to circuitry that lowers the external voltage to the first voltage at a common node. 
     
     
         20 . The method of  claim 19  wherein the circuitry comprises a tap transistor element. 
     
     
         21 . The method of  claim 19  wherein the circuitry comprises a level shift transistor. 
     
     
         22 . The method of  claim 15  wherein the read signal is generated by the controller.