Chip structure and wafer structure

Abstract

A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.

What is claimed is: 
     
         1 . A chip structure, comprising:
 a substrate having a first surface and a second surface opposite to the first surface; and   a stress buffer layer disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.   
     
     
         2 . The chip structure as claimed in  claim 1 , wherein a material of the stress buffer layer comprises metal, glass, or a polymer material. 
     
     
         3 . The chip structure as claimed in  claim 1 , wherein the stress buffer layer protrudes from one of the first surface and the second surface of the substrate. 
     
     
         4 . The chip structure as claimed in  claim 1 , wherein the stress buffer layer is embedded in one of the first surface and the second surface of the substrate. 
     
     
         5 . The chip structure as claimed in  claim 1 , wherein the substrate comprises a plurality of active circuits located on the first surface, and the stress buffer layer is located on an area outside the active circuits. 
     
     
         6 . The chip structure as claimed in  claim 5 , further comprising at least a conductive through hole penetrating the second surface of the substrate and connecting the active circuits. 
     
     
         7 . The chip structure as claimed in  claim 1 , further comprising at least a conductive through hole penetrating the substrate and connecting the first surface and the second surface of the substrate. 
     
     
         8 . A wafer structure, comprising:
 a substrate having a first surface, a second surface opposite to the first surface, and a plurality of cutting paths dividing the substrate into a plurality of chip units; and   a stress buffer layer surrounding each of the chip units and disposed on at least one of the first surface and the second surface of the substrate.   
     
     
         9 . The wafer structure as claimed in  claim 8 , wherein a material of the stress buffer layer comprises metal, glass, or a polymer material. 
     
     
         10 . The wafer structure as claimed in  claim 8 , wherein the stress buffer layer protrudes from one of the first surface and the second surface of the substrate. 
     
     
         11 . The wafer structure as claimed in  claim 8 , wherein the stress buffer layer is embedded in one of the first surface and the second surface of the substrate. 
     
     
         12 . The wafer structure as claimed in  claim 8 , wherein the substrate comprises a plurality of active circuits located on the first surface, and the stress buffer layer is located on an area outside the active circuits. 
     
     
         13 . The wafer structure as claimed in  claim 12 , further comprising a plurality of conductive through holes formed in each of the chip units, wherein the conductive through holes penetrate the second surface of the substrate and connect the active circuits. 
     
     
         14 . The wafer structure as claimed in  claim 8 , further comprising a plurality of conductive through holes formed in each of the chip units, wherein the conductive through holes penetrate the second surface of the substrate and connect the first surface. 
     
     
         15 . The wafer structure as claimed in  claim 14 , further comprising:
 an insulating layer surrounding the conductive through holes; and   an electroplating seed layer covering the insulating layer.   
     
     
         16 . The wafer structure as claimed in  claim 14 , further comprising:
 a plurality of insulating rings surrounding the conductive through holes.   
     
     
         17 . The wafer structure as claimed in  claim 8 , wherein the stress buffer layer is a lattice-like pattern formed by stress buffer rings connected to one another, and the stress buffer rings are integrally formed. 
     
     
         18 . The wafer structure as claimed in  claim 8 , wherein a width of the cutting paths is greater than or equal to a width of the stress buffer layer. 
     
     
         19 . The wafer structure as claimed in  claim 8 , wherein the stress buffer layer is formed by individual stress buffer rings respectively surrounding the chip units. 
     
     
         20 . The wafer structure as claimed in  claim 8 , wherein the cutting paths are defined by an area of the first surface of the substrate which is not covered by a passivation layer, and the area does not include pad regions exposed by the passivation layer.