Method for manufacturing insulated gate field effect transistor

Abstract

An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer.

What is claimed is: 
     
         1 . An insulated gate field effect transistor comprising:
 a base configured to include source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region;   a gate electrode configured to be formed by burying a conducive material layer in the gate electrode formation opening;   a first interlayer insulating layer configured to be formed on the insulating layer and the gate electrode and contain no oxygen atom as a constituent element; and   a second interlayer insulating layer configured to be formed on the first interlayer insulating layer,   wherein the first interlayer insulating layer contains no oxygen atom as a constituent element.   
     
     
         2 . The insulated gate field effect transistor according to  claim 1 , wherein
 the insulating layer includes a lower insulating layer and an upper insulating layer, and   the lower insulating layer covers at least the source/drain regions.   
     
     
         3 . The insulated gate field effect transistor according to  claim 2 , wherein
 the base further includes a side wall film that defines a sidewall of the gate electrode formation opening, and   the lower insulating layer extends on a side surface of the side wall film.