Selective execution for partitioned parallel simulations

Abstract

Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.

What is claimed is: 
     
         1 . A computer-implemented method for design simulation comprising:
 obtaining a high-level design for simulation;   determining a graph representation for the high-level design;   partitioning the graph representation into sub-graphs;   selecting a subset of the sub-graphs for simulation based on input-change bits; and   evaluating the subset of the sub-graphs to produce a simulation result for the high-level design.   
     
     
         2 . The method of  claim 1  further comprising propagating the simulation result, based on the evaluating of the subset of the sub-graphs, to a remainder of the graph representation for further simulation. 
     
     
         3 . The method of  claim 1  wherein the subset of the sub-graphs for simulation is selected based on an input-change bit, for each sub-graph in the subset of the sub-graphs, being set to true. 
     
     
         4 . The method of  claim 1  wherein the partitioning further comprises determining sub-graphs based on levels of logic. 
     
     
         5 . The method of  claim 1  wherein the partitioning into sub-graphs is based on reducing a number of signals crossing sub-graph boundaries. 
     
     
         6 . The method of  claim 1  further comprising using one or more of the input-change bits on a level as part of the selecting of the subset for simulation. 
     
     
         7 . The method of  claim 1  wherein the evaluating is based on an oblivious simulation model. 
     
     
         8 . The method of  claim 7  further comprising allocating processes from the oblivious simulation model to a plurality of processors. 
     
     
         9 . The method of  claim 8  further comprising selectively evaluating the processes based on an input change bit set being set to valid. 
     
     
         10 . The method of  claim 1  wherein the graph representation includes a control data flow graph. 
     
     
         11 . The method of  claim 10  wherein the control data flow graph includes a graph of a combinational region of the high-level design and a state region of the high-level design. 
     
     
         12 . The method of  claim 1  wherein the partitioning includes creating value locality. 
     
     
         13 . The method of  claim 1  wherein the partitioning includes creating event change locality. 
     
     
         14 . The method of  claim 1  wherein the partitioning includes balancing of levels. 
     
     
         15 . The method of  claim 1  wherein the partitioning includes collecting of readers of a simulation value. 
     
     
         16 . The method of  claim 1  wherein the partitioning includes separating primitives evenly across clusters within a level. 
     
     
         17 . The method of  claim 1  wherein the partitioning includes clustering sibling primitives. 
     
     
         18 . The method of  claim 1  further comprising modifying clock gating. 
     
     
         19 . The method of  claim 18  wherein the modifying clock gating includes moving gating to storage elements. 
     
     
         20 . The method of  claim 19  wherein the modifying clock gating includes eliminating a clock gate to a combinational logic portion. 
     
     
         21 . The method of  claim 19  wherein the modifying clock gating is only for simulation purposes. 
     
     
         22 . The method of  claim 18  wherein clock gating is restructured to combine phases and to occur on an active edge of clock. 
     
     
         23 . The method of  claim 1  further comprising determining that an output of one of the sub-graphs has a change of state and copying that change of state to a processor where a process for a second sub-graph uses that change of state as input to the second sub-graph. 
     
     
         24 . The method of  claim 23  further comprising copying a sequence of changes of state for that output of one of the sub-graphs and using the sequence as a series of inputs to the second sub-graph. 
     
     
         25 . The method of  claim 1  further comprising copying the high-level design and simulating the high-level design as well as its copy on at least two different processors. 
     
     
         26 . The method of  claim 25  wherein the copying is performed to accomplish the simulating. 
     
     
         27 . The method of  claim 25  further comprising maintaining primitives with the same function in a single cluster within the copy of the high-level design. 
     
     
         28 . A computer system for design simulation comprising:
 a memory which stores instructions;   one or more processors coupled to the memory wherein the one or more processors are configured to:
 obtain a high-level design for simulation; 
 determine a graph representation for the high-level design; 
 partition the graph representation into sub-graphs; 
 select a subset of the sub-graphs for simulation based on input-change bits; and 
 evaluate the subset of the sub-graphs to produce a simulation result for the high-level design. 
   
     
     
         29 . A computer program product embodied in a non-transitory computer readable medium for design simulation comprising:
 code for obtaining a high-level design for simulation;   code for determining a graph representation for the high-level design;   code for partitioning the graph representation into sub-graphs;   code for selecting a subset of the sub-graphs for simulation based on input-change bits; and   code for evaluating the subset of the sub-graphs to produce a simulation result for the high-level design.