On-chip sensor for measuring dynamic power supply noise of the semiconductor chip

Abstract

An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 functional logic that performs operations with reference to a reference clock signal;   an in-situ probe that receives a delayed clock signal, said delayed clock signal delayed by an amount of time relative to the reference clock signal, and said in-situ probe performs an operation to generate an output signal, wherein the in-situ probe shares a power supply with said functional logic;   a pulse generator that receives the delayed clock signal and the output signal of the in-situ probe, and said pulse generator generates a pulse signal that corresponds to operational delay of the in-situ probe in generating the output signal; and   a sensor that receives the pulse signal and evaluates width of the pulse signal for determining a corresponding dynamic power supply noise fluctuation that was experienced by the functional logic during performance of the operation of the in-situ probe.   
     
     
         2 . The integrated circuit of  claim 1  wherein the in-situ probe comprises stacked inverters. 
     
     
         3 . The integrated circuit of  claim 1  wherein the operation performed by the in-situ probe is to invert the delayed clock 
     
     
         4 . The integrated circuit of  claim 1  wherein the sensor comprises:
 a D flip-flop that receives a reference signal as its D signal and that receives the pulse signal as the flip-flop's clock signal. 
 
     
     
         5 . The integrated circuit of  claim 4  wherein when the reference signal is shorter than the width of the pulse signal, a first value is provided by a Q output of the flip-flop; and wherein when the reference signal exceeds the width of the pulse signal, a different value is provided at the Q output of the flip-flop. 
     
     
         6 . The integrated circuit of  claim 5  further comprising:
 a counter that counts a number of times, over a plurality of clock cycles the reference signal exceeds the width of the pulse signal. 
 
     
     
         7 . The integrated circuit of  claim 6  wherein the number of times the reference signal exceeds the width of the pulse signal is used to form a corresponding cumulative distribution function (CDF). 
     
     
         8 . The integrated circuit of  claim 5  further comprising: a data collector that stores a probability for various offsets the reference signal exceeds the width of the pulse signal. 
     
     
         9 . The integrated circuit of  claim 8  wherein the data collector comprises a shift register and a memory device. 
     
     
         10 . The integrated circuit of  claim 9  wherein the data collector further comprises a data compressor coupled to the shift register and the memory device. 
     
     
         11 . The integrated circuit of  claim 8  wherein the probability is used to form a noise voltage waveform. 
     
     
         12 . The integrated circuit of  claim 1  integrated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. 
     
     
         13 . The integrated circuit of  claim 1 , in which the integrated circuit is integrated into a semiconductor die. 
     
     
         14 . A method comprising:
 receiving, by a digital probe arranged on an integrated circuit, a delayed clock signal, said delayed clock signal delayed by an amount of time relative to a reference clock signal that is referenced fir operation of functional logic included on the integrated circuit;   responsive to the delayed clock signal, performing an operation, by the digital probe, to generate an output signal, wherein operational delay of the digital probe in performing the operation to generate the output signal is sensitive to voltage fluctuation in a power supply of the functional logic included on the integrated circuit;   forming, by logic on the integrated circuit, a signal that corresponds to the operational delay of the digital probe in performing the operation to generate the output signal; and   evaluating, by logic on the integrated circuit, a formed signal for measuring a corresponding voltage fluctuation that was experienced by the functional logic during performance of the operation by the digital probe.   
     
     
         15 . The method of  claim 14  wherein the digital probe shares the power supply with said functional logic. 
     
     
         16 . The method of  claim 14  wherein said forming comprises:
 receiving, by a pulse generator, the delayed clock signal and the output signal of the digital probe; and 
 generating, by said pulse generator, said signal that corresponds to the operational delay of the digital probe in performing the operation to generate the output signal. 
 
     
     
         17 . The method of  claim 15  wherein said operation of the digital probe to generate the output signal comprises:
 inverting the delayed clock signal. 
 
     
     
         18 . The method of  claim 15  further comprising:
 storing said signal in a shift register; and 
 transferring said signals from the shift register to a memo device. 
 
     
     
         19 . The method of  claim 18  further comprising:
 compressing said signals in the shift register before said transferring to the memory device. 
 
     
     
         20 . The method of  claim 14  further comprising:
 adjusting time resolution of the digital probe by controlling a frequency divider coupled to the digital probe. 
 
     
     
         21 . The method of  claim 14  wherein said forming comprises:
 receiving along with the output signal, multiple delay values at a plurality of latch circuits; and 
 collecting data from the digital probe in parallel. 
 
     
     
         22 . The method of  claim 21  further comprising:
 improving meta-stability by coupling additional latch circuits to the plurality of latch circuits and the delayed clock signal. 
 
     
     
         23 . The method of  claim 14  wherein the integrated circuit is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated. 
     
     
         24 . A method comprising the steps of:
 receiving, by a digital probe arranged on an integrated circuit, a delayed clock signal, said delayed clock signal delayed by an amount of time relative to a reference clock signal that is referenced for operation of functional logic included on the integrated circuit;   responsive to the delayed clock signal, performing an operation, by the digital probe, to generate an output signal, wherein operational delay of the digital probe in performing the operation to generate the output signal is sensitive to voltage fluctuation in a power supply of the functional logic included on the integrated circuit;   forming, by logic on the integrated circuit, a signal that corresponds to the operational delay of the digital probe in performing the operation to generate the output signal; and   evaluating, by logic on the integrated circuit, a formed signal for measuring a corresponding voltage fluctuation that was experienced by the functional logic during performance of the operation by the digital probe.   
     
     
         25 . The method of  claim 24  wherein the integrated circuit is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.