Low leakage mim capacitor

Abstract

Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

What is claimed is: 
     
         1 . A container capacitor, comprising:
 a top electrode;   a metal nitride electrode layer as a bottom electrode;   a dielectric layer interposed between the top electrode and the metal nitride electrode layer; and   a metal oxide buffer layer adjacent to the metal nitride electrode layer and interposed between the dielectric layer and the metal nitride electrode layer, wherein a metal in the metal oxide buffer layer matches the metal in the metal nitride electrode layer, and wherein a dielectric constant of the metal oxide buffer layer is greater than a dielectric constant of the dielectric layer.   
     
     
         2 . The container capacitor of  claim 1 , wherein the metal component of the metal oxide buffer layer and the metal nitride electrode layer is tungsten (W). 
     
     
         3 . The container capacitor of  claim 2 , wherein the metal nitride electrode layer includes W 2 N and is adjacent a tungsten oxide buffer layer that includes WO 3 . 
     
     
         4 . The container capacitor of  claim 1 , wherein the metal component of the metal oxide buffer layer and the metal nitride electrode layer is the same refractory metal. 
     
     
         5 . The container capacitor of  claim 1 , wherein the metal oxide buffer layer includes an orthorhombic crystalline structure. 
     
     
         6 . The container capacitor of  claim 1 , wherein a shape of the container capacitor is substantially cylindrical. 
     
     
         7 . The container capacitor of  claim 1 , wherein the metal nitride electrode includes a closed bottom and sidewalls extending away from the closed bottom, and wherein a cross-section of the sidewalls has a substantially oval shape. 
     
     
         8 . The container capacitor of  claim 1 , wherein an interface between the metal nitride electrode layer and an electrical contact of the metal nitride electrode layer is a refractory metal silicide interface. 
     
     
         9 . The container capacitor of  claim 1 , wherein the metal nitride electrode layer includes a tungsten nitride layer overlying a tungsten silicide layer. 
     
     
         10 . A memory cell comprising a container capacitor and an access transistor, wherein the container capacitor includes:
 a top electrode;   a metal nitride electrode layer as a bottom electrode;   a dielectric layer interposed between the top electrode and the metal nitride electrode layer; and   a metal oxide buffer layer adjacent to the metal nitride electrode layer and interposed between the dielectric layer and the metal nitride electrode layer, wherein a metal in the metal oxide buffer layer matches the metal in the metal nitride electrode layer, and wherein a dielectric constant of the metal oxide buffer layer is greater than a dielectric constant of the dielectric layer.   
     
     
         11 . The memory cell of  claim 10 , wherein the metal in the metal oxide buffer layer and the metal nitride electrode of the container capacitor is tungsten (W). 
     
     
         12 . The memory cell of  claim 11 , wherein the metal nitride electrode layer of the container capacitor includes W 2 N and is adjacent a tungsten oxide buffer layer that includes WO 3 . 
     
     
         13 . The memory cell of  claim 10 , wherein the metal oxide buffer layer of the container capacitor includes an orthorhombic crystalline structure. 
     
     
         14 . The memory cell of  claim 10 , wherein an interface between the metal nitride electrode and an electrical contact of the container capacitor is a refractory metal silicide interface. 
     
     
         15 . The memory cell of  claim 10 , wherein the metal nitride electrode of the container capacitor includes a tungsten nitride layer overlying a tungsten silicide layer. 
     
     
         16 . A memory device, comprising:
 an array of memory cells, wherein at least a portion of the memory cells includes a data storage capacitor having a container structure, wherein the data storage capacitor includes:   a top electrode;   a metal nitride electrode layer as a bottom electrode;   a dielectric layer interposed between the top electrode and the metal nitride electrode layer; and   a metal oxide buffer layer adjacent to the metal nitride electrode layer and interposed between the dielectric layer and the metal nitride electrode layer, wherein a metal in the metal oxide buffer layer matches the metal in the metal nitride electrode layer, and wherein a dielectric constant of the metal oxide buffer layer is greater than a dielectric constant of the dielectric layer.   
     
     
         17 . The memory cell of  claim 16 , wherein the metal in the metal oxide buffer layer and the metal nitride electrode of the data storage capacitor is tungsten (W). 
     
     
         18 . The memory cell of  claim 17 , wherein the metal nitride electrode layer of the data storage capacitor includes W 2 N and is adjacent a tungsten oxide buffer layer that includes WO 3 . 
     
     
         19 . The memory cell of  claim 16 , wherein an interface between the metal nitride electrode and an electrical contact of the data storage capacitor is a refractory metal silicide interface. 
     
     
         20 . The memory cell of  claim 16 , wherein the metal nitride electrode of the data storage capacitor includes a tungsten nitride layer overlying a tungsten silicide layer.