US2013285156A1PendingUtilityA1

Fin field effect transistor with variable channel thickness for threshold voltage tuning

Assignee: IBMPriority: Mar 17, 2011Filed: Jun 25, 2013Published: Oct 31, 2013
Est. expiryMar 17, 2031(~4.6 yrs left)· nominal 20-yr term from priority
H10P 50/695H10D 84/834H10D 84/8311H10D 86/215H10D 86/011H01L 27/0886
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Claims

Abstract

A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit (IC) comprising:
 a first plurality of fin field effect transistors (FINFETs) and a second plurality of FINFETs located on a buried oxide substrate, the first plurality of FINFETs having a first channel thickness corresponding to a first threshold voltage, and the second plurality of FINFETs having a second channel thickness corresponding to a second threshold voltage, wherein the first channel thickness is different from the second channel thickness, and the first threshold voltage is different from the second threshold voltage; and   each of the first and second plurality of FINFETs comprising an etched silicon fin, an etched oxide material atop the etched silicon fin, and an etched spacer material atop the etched oxide material.   
     
     
         2 . The IC of  claim 1 , wherein the first threshold voltage and the second threshold voltage range from about 150 millivolts to about 300 millivolts. 
     
     
         3 . The IC of  claim 1 , wherein the thickness of the first plurality of FINFETs and the thickness of the second plurality of FINFETs range from about 1 nanometer to about 12 nanometers. 
     
     
         4 . The IC of  claim 1 , further comprising a third plurality of FINFETs having a third channel thickness corresponding to a third threshold voltage, the third channel thickness and the third threshold voltage being different from the first and second channel thicknesses and the first and second threshold voltages.

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