Display device, array substrate, and thin film transistor

Abstract

Embodiments of the present invention relate to a display device, an array substrate, and a thin film transistor. The thin film transistor comprises a gate, an active layer and a gate insulating layer disposed between the gate and the active layer, the active layer is an oxide semiconductor, and the gate insulating layer comprises at least one layer of inorganic insulating thin film. With the gate insulating layer of the thin film transistor, it is possible that an adverse effect on the oxide semiconductor given by hydrogen-containing groups is effectively avoided, stability of the whole TFT device is enhanced to the most extent, and yield of final products is increased.

What is claimed is: 
     
         1 . A thin film transistor, comprising:
 a gate, an active layer and a gate insulating layer disposed between the gate and the active layer,   wherein the active layer is an oxide semiconductor, and the gate insulating layer comprises at least one layer of inorganic insulating thin film.   
     
     
         2 . The thin film transistor according to  claim 1 , wherein the gate insulating layer is a single layer which is a first gate insulating layer. 
     
     
         3 . The thin film transistor according to  claim 2 , wherein the first gate insulating layer is a silicon dioxide thin film, a silicon nitride thin film, a silicon oxynitride thin film, an aluminum oxide thin film or a titanium oxide thin film. 
     
     
         4 . The thin film transistor according to  claim 2 , wherein the first gate insulating layer is an insulating layer subjected to an annealing process. 
     
     
         5 . The thin film transistor according to  claim 2 , wherein the first gate insulating layer has a thickness of 100 nm˜300 nm. 
     
     
         6 . The thin film transistor according to  claim 1 , wherein the gate insulating layer is in a double-layer structure comprising a first gate insulating layer next to the gate and a second gate insulating layer next to the active layer,
 wherein at least one of the first gate insulating layer and the second gate insulating layer is an inorganic insulating thin film.   
     
     
         7 . The thin film transistor according to  claim 6 , wherein each of the first gate insulating layer and the second gate insulating layer is an inorganic insulating thin film. 
     
     
         8 . The thin film transistor according to  claim 6 , wherein the first gate insulating layer is a silicon nitride thin film or a silicon oxynitride thin film. 
     
     
         9 . The thin film transistor according to  claim 6 , wherein the second gate insulating layer is a silicon oxide thin film, a yttrium oxide thin film or a silicon oxynitride thin film. 
     
     
         10 . The thin film transistor according to  claim 6 , wherein at least the first gate insulating layer of the first and second gate insulating layers is an insulating layer subjected to an annealing process. 
     
     
         11 . The thin film transistor according to  claim 6 , wherein the first gate insulating layer has a thickness of 100 nm˜300 nm. 
     
     
         12 . The thin film transistor according to  claim 6 , wherein the second gate insulating layer has a thickness of 100 nm˜200 nm. 
     
     
         13 . The thin film transistor according to  claim 1 , wherein the gate insulating layer is in a three-layer structure comprising a first gate insulating layer next to the gate, a second gate insulating layer, and a third gate insulating layer next to the active layer, and the second gate insulating layer is located between the first gate insulating layer and the third gate insulating layer,
 wherein at least one of the first gate insulating layer, the second gate insulating layer and the third gate insulating layer is an inorganic insulating thin film.   
     
     
         14 . The thin film transistor according to  claim 13 , wherein each of the first gate insulating layer, the second gate insulating layer and the third gate insulating layer is an inorganic insulating thin film. 
     
     
         15 . The thin film transistor according to  claim 13 , wherein the first gate insulating layer is a silicon nitride thin film or a silicon oxynitride thin film. 
     
     
         16 . The thin film transistor according to  claim 13 , wherein the second gate insulating layer is a silicon oxynitride thin film. 
     
     
         17 . The thin film transistor according to  claim 13 , wherein the third gate insulating layer is a silicon oxide thin film, an aluminum oxide thin film, or a titanium oxide thin film. 
     
     
         18 . The thin film transistor according to  claim 13 , wherein the first gate insulating layer has a thickness of 100 nm˜200 nm. 
     
     
         19 . The thin film transistor according to  claim 13 , wherein the second gate insulating layer has a thickness of 100 nm˜200 nm. 
     
     
         20 . The thin film transistor according to  claim 13 , wherein the third gate insulating layer has a thickness of 100 nm˜150 nm. 
     
     
         21 . The thin film transistor according to  claim 1 , wherein the gate is formed of Cu or Cu alloy. 
     
     
         22 . An array substrate, comprising the thin film transistor according to  claim 1 . 
     
     
         23 . A display device, comprising the array substrate claimed as  claim 22 .