Electronic component allowing the decoding of a radiofrequency transmission channel conveying coded digital information, in particular for satellite digital telebroadcasting

Abstract

The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

1 - 12 . (canceled) 
     
     
         13 . A satellite signal receiver comprising:
 an antenna; and   an integrated circuit (IC) coupled to said antenna and comprising   a tuner having zero intermediate frequency and configured to receive analog signals containing information coded by a digital modulation and comprising a plurality of channels extending over a frequency range, determine a selected channel from among the plurality thereof, and output two phase quadrature baseband signals containing information of the selected channel and information of at least one channel adjacent the selected channel; and   a channel decoder coupled to said tuner.   
     
     
         14 . The satellite signal receiver according to  claim 13  wherein said tuner comprises:
 a signal input coupled to said antenna; 
 an analog block coupled to said signal input comprising a frequency mixer and an analog filter coupled thereto; and 
 an analog-to-digital converter (ADC) coupled to said analog block. 
 
     
     
         15 . The satellite signal receiver according to  claim 14  wherein said channel decoder comprises:
 a demodulator; 
 a digital filter coupled to said demodulator and configured to remove the information of the at least one adjacent channel; and 
 an error correction block configured to deliver a stream of data packets corresponding to the information of the selected channel. 
 
     
     
         16 . The satellite signal receiver according to  claim 15  wherein said analog filter has a top cutoff frequency that is twenty percent higher than a frequency half-width of at least one of the plurality of channels; wherein said ADC has a sampling frequency that is 2.5 times higher than the top cutoff frequency of the analog filter; and wherein said digital filter has a cutoff frequency equal to the frequency half-width of at least one of the plurality of channels. 
     
     
         17 . The satellite signal receiver according to  claim 15  wherein said ADC has a sampling frequency that varies as a function of a central frequency, Fd, of the selected channel to reduce harmonics of the sampling frequency from a frequency span of Fd−F2 to Fd+F2, where F2 designates the top cutoff frequency of said analog filter. 
     
     
         18 . The satellite signal receiver according to  claim 13  further comprising a metal plate and an adhesive layer securing said metal layer to said IC. 
     
     
         19 . The satellite signal receiver according to  claim 13  wherein said IC includes an insulated portion having a first conductivity and an insulating barrier having a second conductivity, said insulating barrier insulating said insulated portion from remaining portions of said monolithic substrate;
 wherein at least the decoder is formed in the insulated portion; 
 and wherein said insulating barrier is biased by a bias voltage different from that of said insulated portion. 
 
     
     
         20 . The satellite signal receiver according to  claim 15  wherein said analog filter comprises a bandpass filter having a bottom cutoff frequency with a value greater than 0;
 further comprising a controllable generator configured to deliver a mixing signal to said frequency mixer having a frequency being below a central frequency of the selected channel by an offset value at least equal to the bottom cutoff frequency; and wherein said demodulator is configured to correct phase noise, frequency drift and the offset value. 
 
     
     
         21 . The satellite signal receiver according to  claim 15  wherein said analog block module comprises a first controlled-gain amplifier with a controlled gain coupled between said signal input and said frequency mixer; and wherein said tuner further comprises a digital block coupled to said analog block by said ADC. 
     
     
         22 . An integrated circuit (IC) comprising:
 a tuner having zero intermediate frequency and configured to receive analog signals containing information coded by a digital modulation and comprising a plurality of channels extending over a frequency range, determine a selected channel from among the plurality thereof, and output two phase quadrature baseband signals containing information of the selected channel and information of at least one channel adjacent the selected channel; and   a channel decoder coupled to said tuner.   
     
     
         23 . The IC according to  claim 22  wherein said tuner comprises:
 a signal input coupled to said antenna; 
 an analog block coupled to said signal input comprising a frequency mixer and an analog filter coupled thereto; and 
 an analog-to-digital converter (ADC) coupled to said analog block. 
 
     
     
         24 . The IC according to  claim 23  wherein said channel decoder comprises:
 a demodulator; 
 a digital filter coupled to said demodulator and configured to remove the information of the at least one adjacent channel; and 
 an error correction block configured to deliver a stream of data packets corresponding to the information of the selected channel. 
 
     
     
         25 . The IC according to  claim 24  wherein said analog filter has a top cutoff frequency that is twenty percent higher than a frequency half-width of at least one of the plurality of channels; wherein said ADC has a sampling frequency that is 2.5 times higher than the top cutoff frequency of the analog filter; and wherein said digital filter has a cutoff frequency equal to the frequency half-width of at least one of the plurality of channels. 
     
     
         26 . The IC according to  claim 24  wherein said ADC has a sampling frequency that varies as a function of a central frequency, Fd, of the selected channel to reduce harmonics of the sampling frequency from a frequency span of Fd−F2 to Fd+F2, where F2 designates the top cutoff frequency of said analog filter. 
     
     
         27 . The IC according to  claim 24  wherein said analog filter comprises a bandpass filter having a bottom cutoff frequency with a value greater than 0; further comprising a controllable generator configured to deliver a mixing signal to said frequency mixer having a frequency being below a central frequency of the selected channel by an offset value at least equal to the bottom cutoff frequency; and wherein said demodulator is configured to correct phase noise, frequency drift and the offset value. 
     
     
         28 . The IC according to  claim 24  wherein said analog block module comprises a first controlled-gain amplifier with a controlled gain coupled between said signal input and said frequency mixer; and wherein said tuner further comprises a digital block coupled to said analog block by said ADC. 
     
     
         29 . The IC according to  claim 28  wherein said digital block is configured to compare a mean overall power with a first reference value corresponding to a maximum power desired at a location of said analog block, and adjust a gain of the first controlled-gain amplifier stage as a function of the comparison. 
     
     
         30 . The IC according to  claim 29  wherein said analog block further comprises a second controlled-gain amplifier coupled downstream of said analog filter; and wherein said tuner is configured to calculate a mean power of the selected channel, compare the mean power with a second reference value corresponding to a maximum channel power at the input of said ADC, and adjust a gain of said second controlled-gain amplifier. 
     
     
         31 . A signal processing method using an integrated circuit (IC) comprising a tuner having zero intermediate frequency and a channel decoder coupled thereto, the method comprising:
 operating the tuner to receive analog signals containing information coded by a digital modulation and comprising a plurality of channels extending over a frequency range, determine a selected channel from among the plurality thereof, and output two phase quadrature baseband signals containing information of the selected channel and information of at least one channel adjacent the selected channel; and   operating the channel decoder to deliver a stream of data packets corresponding to the information of the selected channel.   
     
     
         32 . The method according to  claim 31  further comprising operating the channel decoder to remove the information of the at least one adjacent channel, and perform error correction to deliver the stream of data packets.