Vertically stackable dies having chip identifier structures

Abstract

A particular method of making a stacked multi-die semiconductor device includes forming a stack of at least two dies. Each die includes a chip identifier structure that includes a first set of at least two through vias that are each hard wired to a set of external electrical contacts. Each die further includes chip identifier selection logic coupled to the chip identifier structure. Each die further includes a chip select structure that includes a second set of at least two through vias coupled to the chip identifier selection logic. The method further includes coupling each external electrical contact to a voltage source or ground. Each of the first set of through vias has a pad that is coupled to an adjacent through via and each of the second set of through vias is coupled to its own respective pad.

What is claimed is: 
     
         1 . A method of making a stacked multi-die semiconductor device, the method comprising:
 forming a stack of N dies, wherein each die comprises:
 a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts; 
 chip identifier selection logic coupled to the chip identifier structure; and 
 a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one; and 
   coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of N through vias has a pad that is coupled to an adjacent through via and each of the second set of N through vias is coupled to its own respective pad.   
     
     
         2 . The method of  claim 1 , wherein each die further comprises a common access channel structure that comprises a plurality of through vias. 
     
     
         3 . The method of  claim 1 , wherein the stack of the N dies is formed on a package substrate that supplies the voltage source and the ground and the package substrate has a plurality of package balls formed on a side of the package substrate opposite the stack of the N dies, the plurality of package balls comprising at least N chip select package balls coupled to the second set of N through vias in the chip select structure of one die of the stack of N dies. 
     
     
         4 . The method of  claim 3  wherein the stack of N dies comprises a stack of N memory dies. 
     
     
         5 . The method of  claim 1 , wherein the stack of the N dies is formed on a mother die that supplies the voltage source and the ground and the mother die comprises a third set of N through vias coupled to the first set of N through vias the chip identifier structure of one die of the stack of N dies and a fourth set of N through vias coupled to the second set of N through vias in the chip select structure of the one die of the stack of N dies. 
     
     
         6 . The method of  claim 5 , wherein the mother die comprises a logic chip, the stack of N dies comprises a stack of N memory dies, and the fourth set of N through vias is coupled to a memory channel physical layer of the mother die. 
     
     
         7 . The method of  claim 1 , wherein each die of the stack of N dies is substantially the same and the stack of N dies is formed without programming, sorting, marking, or separating each die of the stack of N dies. 
     
     
         8 . The method of  claim 1 , wherein the forming and the coupling are initiated by a processor integrated into an electronic device. 
     
     
         9 . The method of  claim 1 , further comprising integrating the stacked multi-die semiconductor device into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. 
     
     
         10 . A method comprising:
 a first step for forming a stack of N dies, wherein each die comprises:
 a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts; 
 chip identifier selection logic coupled to the chip identifier structure; and 
 a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one; and 
   a second step for coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of the N through vias has a pad that is coupled to an adjacent through via and each of the second set of the N through vias is coupled to its own respective pad.   
     
     
         11 . The method of  claim 10 , wherein the first step and second step are initiated by a processor integrated into an electronic device. 
     
     
         12 . A method comprising:
 receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
 a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one; and 
 a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts; 
   transforming the design information to comply with a file format; and   generating a data file comprising the transformed design information.   
     
     
         13 . The method of  claim 12 , wherein the data file comprises a GDSII format. 
     
     
         14 . A method comprising:
 receiving a data file comprising design information corresponding to a semiconductor device; and   fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
 a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one; and 
 a second die stacked above the first die, the second die comprising a. second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts. 
   
     
     
         15 . The method of  claim 14 , wherein the data file has a GDSII format. 
     
     
         16 . A method comprising:
 receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising a semiconductor structure comprising:
 a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one; and 
 a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts; and 
   transforming the design information to generate a data file.   
     
     
         17 . The method of  claim 16 , wherein the data file has a GERBER format. 
     
     
         18 . A method comprising:
 receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board; and   manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a semiconductor structure comprising:
 a first die comprising a first chip identifier structure that comprises a number N of through vias that are each hard wired to a first set of external electrical contacts, the number N comprising an integer greater than one; and 
 a second die stacked above the first die, the second die comprising a second chip identifier structure that comprises N through vias that are each hard wired to a second set of electrical contacts. 
   
     
     
         19 . The method of  claim 18 , wherein the data file has a GERBER format. 
     
     
         20 . The method of  claim 18 , further comprising integrating the circuit board into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. 
     
     
         21 . A computer-readable tangible medium storing instructions executable by a computer, the instructions comprising:
 instructions that are executable by the computer to initiate forming a stack of N dies, wherein each die comprises:
 a chip identifier structure that comprises a first set of N through vias that are each hard wired to a set of external electrical contacts; 
 chip identifier selection logic coupled to the chip identifier structure; and 
 a chip select structure that comprises a second set of N through vias coupled to the chip identifier selection logic, wherein N is an integer greater than one; and 
   instructions that are executable by the computer to initiate coupling each external electrical contact in each set of external electrical contacts to a voltage source or to ground, wherein each of the first set of the N through vias has a pad that is coupled to an adjacent through via and each of the second set of the N through vias is coupled to its own respective pad.   
     
     
         22 . A method comprising:
 receiving a chip identifier signal based on a position of a first die within a die stack, wherein the chip identifier signal is received at the first die via multiple through vias of the first die;   and determining, based on the received chip identifier signal, whether the first die is a particular die that is indicated by a received chip selection signal.   
     
     
         23 . The method of  claim 22 , wherein a first through via of a chip identifier structure of the first die has a pad that is coupled to a second through via of the chip identifier structure, the second through via adjacent to the first through via, and wherein at least a portion of the chip identifier signal is received at the pad from a first through via of a second die and is conveyed to the second through via of the first die.