Ic output signal path with switch, bus holder, and buffer

Abstract

An electronic integrated circuit includes a signal path connected between the functional logic ( 15 ) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit ( 121 B), and an output buffer ( 19 ).

What is claimed is: 
     
         1 . An integrated circuit comprising:
 A. functional logic having a functional output lead and a control output lead;   B. a three state output buffer having an input, an output lead, and a control input;   C. a serial in data lead;   D. a first multiplexer having an output, a first input coupled to the functional output lead, and a second input coupled to the serial in data lead;   E. a first memory circuit having an input coupled to the output of the first multiplexer and having an output coupled to the input of the three sate output buffer;   F. a second multiplexer having an output, a first input coupled to the control output lead, and a second input coupled to the output of the first memory circuit;   G. a second memory circuit having an output and an input coupled to the output of the second multiplexer;   H. a serial out data lead coupled to the output of the second memory circuit; and   I. a latching control buffer having an input coupled to the output of the second memory circuit, a control input, and an output coupled to the control input of the three state output buffer.   
     
     
         2 . The integrated circuit of  claim 1  in which the latching control buffer includes a switch circuit having a control lead coupled to the control input. 
     
     
         3 . The integrated circuit of  claim 1  in which the latching control buffer includes a switch circuit having an input coupled to the control output lead of the functional logic, a control lead coupled to the control input, and a switch output, and including an output buffer circuit coupled between the switch output and the output of the latching control buffer, and including an input buffer coupled between the switch circuit output and the output of the latching control buffer. 
     
     
         4 . The integrated circuit of  claim 1  in which the latching control buffer includes a switch circuit having an input coupled to the control output lead of the functional logic, a control lead coupled to the control input, and a switch output, and including an output buffer circuit coupled between the switch output and the output of the latching control buffer, and including an input buffer coupled between the switch circuit output and the output of the latching control buffer, the input buffer being weaker than the output buffer circuit.