Vertically stackable dies having chip identifier structures

Abstract

A particular device includes a first die that includes a portion of a chip identifier structure, the portion including a first set of at least two through vias that are each connected to a corresponding external electrical contact of a first set of external electrical contacts. Each of the first set of through vias has a pad configured to be coupled to an adjacent through via of a second die in the chip identifier structure. Each external electrical contact of the first set of external electrical contacts is configured to transmit a chip select signal. The first die further includes at least a portion of a chip communication structure including a second set of at least one through via. Each via of the second set is connected to one external electrical contact of a second set of external electrical contacts.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first die comprising:
 a portion of a chip identifier structure, the portion of the chip identifier structure comprising a first set of at least two through vias that are each connected to a corresponding external electrical contact of a first set of external electrical contacts, wherein each of the first set of through vias has a pad configured to be coupled to an adjacent through via of a second die in the chip identifier structure, and wherein each external electrical contact of the first set of external electrical contacts is configured to transmit a chip select signal; and 
 at least a portion of a chip communication structure comprising a second set of at least one through via, wherein each via of the second set is connected to one external electrical contact of a second set of external electrical contacts. 
   
     
     
         2 . The semiconductor device of  claim 1 , further comprising chip identification decoding logic on the first die, wherein the chip identification decoding logic is coupled to the chip identifier structure. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising an interface to a host device. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the host device is a separate device or a mother die. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the interface to the host device is connected to the first set of external electrical contacts. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first die and the second die comprise structurally identical circuitry, and wherein the first set of through vias of the first die are coupled to corresponding through vias of the second die. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the second die is stacked above the first die. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising a device selected from at least one of: a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, or a computer, into which the first die is integrated. 
     
     
         9 . A method comprising:
 forming a first die, wherein the first die comprises:
 a portion of a chip identifier structure, the portion of the chip identifier structure comprising a first set of at least two through vias that are each connected to a corresponding external electrical contact of a first set of external electrical contacts, wherein each of the first set of through vias has a pad configured to be coupled to an adjacent through via of a second die in the chip identifier structure, and wherein each external electrical contact of the first set of external electrical contacts is configured to transmit a chip select signal; and 
 at least a portion of a chip communication structure comprising a second set of at least one through via, wherein each via of the second set is connected to one external electrical contact of a second set of external electrical contacts. 
   
     
     
         10 . The method of  claim 9 , wherein the first die further comprises chip identification decoding logic, wherein the chip identification decoding logic is coupled to the chip identifier structure. 
     
     
         11 . The method of  claim 9 , wherein at least one through via of the first set of through vias transmits a different signal than other through vias of the first set of through vias. 
     
     
         12 . The method of  claim 9 , wherein the first die further comprises an interface to a host device. 
     
     
         13 . The method of  claim 12 , wherein the host device is a separate device or a mother die. 
     
     
         14 . The method of  claim 12 , wherein the interface to the host device is connected to the first set of external electrical contacts. 
     
     
         15 . The method of  claim 9 , further comprising coupling the first set of through vias of the first die to corresponding through vias of the second die, wherein the first die and the second die comprise structurally identical circuitry. 
     
     
         16 . The method of  claim 15 , further comprising stacking the second die above the first die. 
     
     
         17 . The method of  claim 9 , wherein forming the first die is initiated by a processor integrated into an electronic device. 
     
     
         18 . An apparatus comprising:
 a first die comprising:
 a portion of means for identifying a chip, the portion of means for identifying comprising a first set of at least two through vias that are each connected to a corresponding means for making external electrical contact of a first set of means for making external electrical contact, wherein each of the first set of through vias has a connection means configured to be coupled to an adjacent through via of a second die in the means for identifying a chip, and wherein each means for making external electrical contact of the first means for making external electrical contacts is configured to transmit a chip select signal; and 
 means for communication comprising a second set of at least one through via, wherein each via of the second set is connected to one means for making external electrical contact of a second set of means for making external electrical contact. 
   
     
     
         19 . The apparatus of  claim 18 , wherein the first die and the second die comprise structurally identical circuitry, and wherein the first set of through vias of the first die are coupled to corresponding through vias of the second die. 
     
     
         20 . The apparatus of  claim 18 , further comprising a device selected from at least one of: a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, or a computer, into which the first die is integrated.