Power device and fabricating method thereof

Abstract

A power device, which has a Field Stop (FS) layer based on a semiconductor substrate between a collector region and a drift region in an FS-IGBT structure, wherein the thickness of the FS layer and the impurity density of the collector region are easy to adjust and the FS layer has an improved function, and a fabricating method thereof.

1 . A power device, comprising:
 a semiconductor substrate of a first conductivity type;   a Field Stop (FS) layer of a the first conductivity type disposed on the semiconductor substrate, the FS layer having a section having an impurity density higher than an impurity density of the semiconductor substrate;   a drift region of an epitaxial layer of the first conductivity type disposed on the FS layer and having an impurity density lower than the impurity density of the semiconductor substrate;   a base region of a second conductivity type disposed in an upper portion of the drift region;   an emitter region of the first conductivity type disposed in an upper portion of the base region;   a gate electrode on a gate insulation layer, the gate insulation layer is disposed on the drift region, the base region, and the emitter region; and   a collector region of the second conductivity type disposed below the semiconductor substrate.   
     
     
         2 . The power device of  claim 1 , wherein the FS layer has a maximum impurity density at a first section, an impurity density of the FS layer increases from the semiconductor substrate to the first section and decreases from the first section to the drift region. 
     
     
         3 . The power device of  claim 2 , wherein the impurity density rapidly decreases at a portion of the FS layer, the portion of the FS layer contacts the drift region. 
     
     
         4 . The power device of  claim 1 , wherein the FS layer includes at least two layers with different impurities. 
     
     
         5 . The power device of  claim 4 , wherein the at least two layers includes a first layer adjacent to the semiconductor substrate, the first layer has an impurity density higher than an impurity density of a second layer from the at least two layers. 
     
     
         6 . The power device of  claim 4 , wherein the at least two layers includes a layer adjacent to the drift region, the layer has an impurity density lower than the impurity density of the semiconductor substrate. 
     
     
         7 . The power device of  claim 1 , wherein each of the semiconductor substrate and the drift region has a constant impurity density profile along a depth direction, the semiconductor substrate has the impurity density higher than the impurity density of the drift region, and the FS layer cancels a density difference between the semiconductor substrate and the drift region, and has a portion with an impurity density higher than the impurity density of the semiconductor substrate. 
     
     
         8 . The power device of  claim 1 , wherein the semiconductor substrate has an impurity density of about 1E14 cm −3  to about 1E16 cm −3 , and the FS layer includes a portion having an impurity density of about 1E15 cm −3  to about 1E17 cm −3 . 
     
     
         9 . The power device of  claim 1 , further comprising:
 an emitter electrode electrically connected to the emitter region; and   a collector electrode electrically connected to the collector region.   
     
     
         10 . The power device of  claim 1 , wherein the semiconductor substrate includes a Czochralski (CZ) single-crystal. 
     
     
         11 . A method of fabricating a power device, the method comprising:
 preparing a semiconductor substrate of a first conductivity type;   forming a second Field Stop (FS) layer by implanting impurity ions io the first conductivity type in an upper surface of the semiconductor substrate;   forming a drift region by growing an epitaxial layer of the first conductivity type, which has an impurity density lower than an impurity density of the semiconductor substrate, on the second FS layer;   forming a base region of a second conductivity type in a section of the surface of the drift region;   forming an emitter region of the first conductivity type in a section of the surface of the base region;   forming a gate insulation layer on the drift region, the base region, and the emitter region;   forming a gate electrode on the gate insulation layer;   forming an emitter electrode on the base region and on the emitter region;   forming a first FS layer by grinding a lower surface of the semiconductor substrate; and   forming a collector region below the first FS layer.   
     
     
         12 . The method of  claim 11 , wherein a sum of a thickness of the second FS layer and a thickness of the first FS layer is less than the thickness of the first FS layer when the second FS layer is not formed. 
     
     
         13 . The method of  claim 11 , wherein the forming the second FS layer includes diffusing the impurity ions by a heat treatment after implanting the impurity ions. 
     
     
         14 . The method of  claim 11 , wherein the second FS layer includes at least two layers formed with different impurities or different doping energies. 
     
     
         15 . The method of  claim 14 , wherein the at least two layers includes a first layer adjacent to the first FS layer, the first layer has an impurity density higher than an impurity density of a second layer from the at least two layers. 
     
     
         16 . The method of  claim 11 , wherein each of the first FS layer and the drift layer has a constant impurity density profile along a depth direction, the first FS layer has an impurity density higher than an impurity density of the drift layer, and the second FS layer includes a region having an impurity density higher than an impurity density of the first FS layer, the impurity density of the second FS layer increases and then decreases to cancel a density difference between the first FS layer and the drift layer. 
     
     
         17 . The method of  claim 11 , wherein the first FS layer has an impurity density of about 1E14 cm −3  to about 1E16 cm −3 , and the second FS layer includes a portion having an impurity density of about 1E15 cm 3  to about 1E17 cm −3 . 
     
     
         18 . The method of  claim 11 , wherein each of the base region and the emitter region is formed by selectively implanting corresponding ions in a predetermined part and diffusing the implanted ions by a heat treatment, and the collector region is formed by implanting corresponding ions into the lower surface of the semiconductor substrate, after the grinding of the semiconductor substrate, and diffusing the implanted ions by a heat treatment. 
     
     
         19 . A power device comprising:
 a first Field Stop (FS) layer based on a semiconductor substrate of a first conductivity type and having an impurity density that is constant along a depth direction;   a second FS layer of the first conductivity type which is disposed on the first FS layer, has an impurity density that is variable along the depth direction, and has a peak impurity density area higher than the impurity density of the first FS layer; and   a drift region of an epitaxial layer of the first conductivity type disposed on the second FS layer.   
     
     
         20 . The power device of  claim 19 , wherein the drift region has a constant impurity density along the depth direction and has an impurity density less than the impurity density of the first FS layer.