Etch stop layer formation in metal gate process

Abstract

A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric layer having a U-shaped geometry in contact with the channel portion of the semiconductor substrate and a metal gate conductor comprised of a catalytic metal;   a gate dielectric cap having edges that are substantially self-aligned to sidewalls of the metal gate conductor, wherein the gate dielectric cap is an oxide-containing dielectric having a self-limited thickness of less than 20 nm;   a source region and a drain region on opposing sides of the gate structure; and   a contact to each of the source region and the drain region, wherein the contact is separated from the metal gate conductor by at least the gate dielectric cap.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the at least one gate dielectric layer is comprised of a high-k dielectric material. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the at least one gate dielectric layer has a thickness that ranges 0.8 mm to 6.0 mm. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the high-k dielectric material is selected from the group consisting of HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3  and mixtures thereof. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the gate dielectric cap comprises at least one of silicon-oxycarbide (SiCO), silicon carbon nitro-oxide (SiCNO) and silicon oxide (SiO 2 ). 
     
     
         6 . The semiconductor device of  claim 1 , wherein the catalytic metal comprises aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) or a combination thereof. 
     
     
         7 . The semiconductor device of  claim 1 , wherein a spacer is adjacent to the gate structure. 
     
     
         8 . The semiconductor device of  claim 4 , wherein said edges of the gate dielectric cap that are substantially self-aligned to sidewalls of the metal gate conductor may extend past the metal gate conductor over the spacer by a dimension of 20 nm or less. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the gate structure of the semiconductor device and an adjacent gate structure of an adjacent semiconductor device are separated by a pitch ranging from 30 nm to 100 nm. 
     
     
         10 . The semiconductor device of  claim 1  further comprising dielectric spacers adjacent to the gate structure, wherein the material of the gate dielectric cap is not present on an exterior surface of the dielectric spacers. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the catalytic metal is aluminum, the interface oxide is aluminum oxide (Al 2 O 3 ), and the gate dielectric cap is silicon oxide (SiO 2 ). 
     
     
         12 . The semiconductor device of  claim 1 , wherein at least one contact of said contact to each of the source region and the drain region is in direct contact with the gate dielectric cap. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the at least one contact is comprised of titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, or alloys thereof.