Semiconductor device and method for manufacturing same

Abstract

A semiconductor device ( 1001 ) includes a thin-film transistor ( 103 ) including a gate electrode ( 3 a ), source and drain electrodes ( 13 as, 13 ad ), and an oxide semiconductor layer ( 7 ), and a source bus line ( 13 s ). The source electrode, the source bus line and the drain electrode include a first metallic element and the oxide semiconductor layer includes a second metallic element. When viewed along a normal to its substrate, at least respective portions of the source electrode, the source bus line, and the drain electrode overlap with the oxide semiconductor layer. A low reflecting layer ( 4 s, 4 d ) which includes the first and second metallic elements and which has a lower reflectance to visible radiation than the source electrode has been formed between the source electrode and the oxide semiconductor layer, between the source bus line and the oxide semiconductor layer, and between the drain line and the oxide semiconductor layer.

1 . A semiconductor device comprising a substrate and a thin-film transistor which is supported on the substrate,
 wherein the thin-film transistor includes:   an oxide semiconductor layer which includes a channel region and a source contact region and a drain contact region that are located on right- and left-hand sides of the channel region;   a gate electrode which is arranged between the substrate and the oxide semiconductor layer so as to overlap with at least the channel region of the oxide semiconductor layer;   a gate insulating layer which has been formed between the gate electrode and the oxide semiconductor layer;   a source electrode which is electrically connected to the source contact region; and   a drain electrode which is electrically connected to the drain contact region, and   wherein the source electrode is electrically connected to a source bus line, and   wherein the source electrode, the source bus line and the drain electrode include a first metallic element and the oxide semiconductor layer includes a second metallic element, and   wherein when viewed along a normal to the substrate, at least respective portions of the source electrode, the source bus line, and the drain electrode overlap with the oxide semiconductor layer, and   wherein a low reflecting layer which includes the first and second metallic elements and which has a lower reflectance to visible radiation than the source electrode has been formed between the source electrode and the oxide semiconductor layer, between the source bus line and the oxide semiconductor layer, and between the drain electrode and the oxide semiconductor layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the second metallic element is indium and the low reflecting layer includes indium metal. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the low reflecting layer is a reaction layer which has been formed through oxidation of the first metallic element and reduction of the second metallic element which have been caused by a reaction between the source electrode, the source bus line, and the drain electrode and the oxide semiconductor layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the respective lower surfaces of the source electrode, the source bus line and the drain electrode are entirely in contact with the low reflecting layer. 
     
     
         5 . The semiconductor device of  claim 1 , wherein when viewed along a normal to the substrate, the low reflecting layer is extended from one end of the source electrode that faces the channel region toward the drain electrode by a distance Ds to partially cover the channel region and also extended from one end of the drain electrode that faces the channel region toward the source electrode by a distance Dd to partially cover the channel region, and wherein the sum of these distances Ds and Dd is smaller than a channel length. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the distances Ds and Dd are both 0.1 μm to 1.0 μm. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising an etch stop which covers at least the channel region of the oxide semiconductor layer. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising a first interlayer insulating layer which covers the source electrode, the source bus line and the drain electrode, and
 wherein the low reflecting layer is obtained by forming the source electrode, the source bus line, and the drain electrode on the oxide semiconductor layer, forming the first interlayer insulating layer which covers the source electrode, the source bus line, and the drain electrode and then performing an annealing process at a temperature of 200° C. to 400° C.   
     
     
         9 . The semiconductor device of  claim 1 , further comprising a backlight which is arranged at the rear of the substrate. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the first metallic element is titanium, the oxide semiconductor layer includes an In—Ga—Zn—O based semiconductor, and the second metallic element is indium. 
     
     
         11 . A liquid crystal display device including the semiconductor device of  claim 1 , the display device comprising:
 a counter substrate which is arranged to face the substrate;   a liquid crystal layer which is interposed between the substrate and the counter substrate; and   a seal portion which is made of a seal member including a photocurable resin and which surrounds the liquid crystal layer, and   wherein the liquid crystal display device has a display area with a plurality of pixels and a frame area which is located around the periphery of the display area, the thin-film transistor is arranged in the display area, and the seal portion is arranged in the frame area, and   wherein in the frame area, a light absorbing layer which absorbs light to cure the seal member has been formed between the seal portion and the display area on the substrate, and   an opaque layer has been formed between the seal portion and the display area on the counter substrate, and   the light absorbing layer is an oxide semiconductor layer which has been formed of the same oxide semiconductor film as the oxide semiconductor layer of the thin-film transistor.   
     
     
         12 . A liquid crystal display device including the semiconductor device of  claim 1 , the display device comprising:
 a counter substrate which is arranged to face the substrate;   a liquid crystal layer which is interposed between the substrate and the counter substrate; and   a seal portion which is made of a seal member including a photocurable resin and which surrounds the liquid crystal layer, and   wherein the liquid crystal display device has a display area with a plurality of pixels and a frame area which is located around the periphery of the display area, the thin-film transistor is arranged in the display area, and the seal portion is arranged in the frame area, and   wherein in the frame area, a light reflecting layer which reflects light to cure the seal member has been formed on the substrate so as to partially overlap with the seal portion, and   an opaque layer has been formed on the counter substrate so as to partially overlap with the seal portion and to face the light reflecting layer, and   the light reflecting layer is a metal layer which has been formed of the same metal film as the source electrode, and between the metal layer and the substrate, stacked in this order on the substrate are a light absorbing layer which is formed of the same oxide semiconductor film as the oxide semiconductor layer of the thin-film transistor and a layer which includes the first and second metallic elements and which has a lower reflectance to the light than the metal layer.   
     
     
         13 . The liquid crystal display device of  claim 12 , wherein a portion of the light absorbing layer is located between the seal portion and the display area and is not covered with the metal layer. 
     
     
         14 . The liquid crystal display device of  claim 11 , wherein the seal portion has a gap through which a liquid crystal material is injected, and
 wherein the display device further includes a gap closing portion which is made of a photocurable resin and which is used to close the gap, and   wherein the light absorbing layer is also arranged between the gap closing portion and the display area.   
     
     
         15 . The liquid crystal display device of  claim 12 , wherein the seal portion has a gap through which a liquid crystal material is injected, and
 wherein the display device further includes a gap closing portion which is used to close the gap, and   wherein the light reflecting layer is arranged to overlap with the gap closing portion, too.   
     
     
         16 . A method for fabricating a semiconductor device, the method comprising the steps of:
 (A) forming a gate electrode on a substrate;   (B) forming a gate insulating layer to cover the gate electrode;   (C) forming an oxide semiconductor layer on the gate insulating layer;   (D) forming, on the oxide semiconductor layer, a source electrode, a source bus line which is connected to the source electrode, and a drain electrode which is electrically isolated from the source electrode;   (E) forming a first interlayer insulating layer to cover the source electrode, the source bus line and the drain electrode; and   (F) performing an annealing process at a temperature of 200° C. to 400° C., thereby forming a low reflecting layer, of which the reflectance to visible radiation is lower than that of the source electrode, between the source electrode, the source bus line, and the drain electrode and the oxide semiconductor layer.   
     
     
         17 . The method of  claim 16 , further comprising the step of forming an etch stop to cover a portion of the oxide semiconductor layer to be a channel region between the steps (C) and (D). 
     
     
         18 . A method for fabricating a semiconductor device, the method comprising the steps of:
 (A) forming a gate electrode on a substrate;   (B) forming a gate insulating layer to cover the gate electrode;   (C) depositing an oxide semiconductor film and a metal film in this order on the gate insulating layer and patterning a stack of the two films, thereby obtaining an oxide semiconductor layer and a metal layer having the same pattern as the oxide semiconductor layer;   (D) patterning the metal layer, thereby forming a source electrode, a source bus line which is connected to the source electrode, and a drain electrode which is electrically isolated from the source electrode, out of the metal layer;   (E) forming a first interlayer insulating layer to cover the source electrode, the source bus line and the drain electrode; and   (F) performing an annealing process at a temperature of 200° C. to 400° C., thereby forming a low reflecting layer, of which the reflectance to visible radiation is lower than that of the source electrode, between the source electrode, the source bus line, and the drain electrode and the oxide semiconductor layer.   
     
     
         19 . The method of  claim 16 , wherein the metal film includes a titanium film and the oxide semiconductor layer includes an In—Ga—Zn—O based semiconductor. 
     
     
         20 . The method of  claim 19 , wherein in the step (F), the annealing process is performed at a temperature of 350° C. to 400° C.