Multi-layered semiconductor apparatus

Abstract

Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus ( 100 ) includes a plurality of layered semiconductor chips ( 20 - 1, 20 - 2 ) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus ( 100 ) further comprises a heat releasing section ( 50 ) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

1 - 51 . (canceled) 
     
     
         52 . An apparatus comprising:
 a semiconductor chip including a plurality of circuit regions;   wherein a difference in temperature within the semiconductor chip is reduced as a result of a controlled access to each of the plurality of circuit regions.   
     
     
         53 . The apparatus of  claim 52 , further comprising a second semiconductor chip coupled with the semiconductor chip to form a semiconductor stack, the plurality of circuit regions including a second plurality of circuit regions of the second semiconductor chip, wherein a difference in temperature within the semiconductor stack is reduced as a result of the controlled access. 
     
     
         54 . The apparatus of  claim 52 , wherein at least one of a frequency or a duration of access to each of the plurality of circuit regions is controlled. 
     
     
         55 . The apparatus of  claim 52 , wherein the semiconductor chip includes a dummy circuit region, and the controlled access includes accessing the dummy circuit region to decrease heat deformation of the semiconductor chip. 
     
     
         56 . The apparatus of  claim 52 , further comprising a heat releasing section coupled with the semiconductor chip, wherein the plurality of circuit regions includes a first circuit region and a second circuit region having a substantially similar function to the first circuit region, the first circuit region positioned closer to the heat releasing section, and the controlled access including allocating a greater access time to the first circuit region. 
     
     
         57 . An apparatus comprising:
 a semiconductor chip including a plurality of circuit regions;   wherein a difference in temperature within the semiconductor chip is reduced as a result of an arrangement of the plurality of circuit regions.   
     
     
         58 . The apparatus of  claim 57 , further comprising a second semiconductor chip coupled with the semiconductor chip to form a semiconductor stack, the plurality of circuit regions including a second plurality of circuit regions of the second semiconductor chip, wherein a difference in temperature within the semiconductor stack is reduced as a result of the arrangement. 
     
     
         59 . The apparatus of  claim 57 , wherein the arrangement includes separating a first circuit region of the plurality of circuit regions from a second circuit region of the plurality of circuit regions, the first circuit region and the second circuit region being accessed during the same time period. 
     
     
         60 . The apparatus of  claim 57 , wherein the arrangement includes a first circuit region of the plurality of circuit regions misaligned with a second circuit region of the plurality of circuit regions, the first circuit region and the second circuit region being accessed during the same time period. 
     
     
         61 . The apparatus of  claim 57 , wherein the arrangement includes a first circuit region of the plurality of circuit regions that is separated from a second circuit region of the plurality of circuit regions by a third circuit region of the plurality of circuit regions, the second circuit region being accessed during the same time period as the first circuit region. 
     
     
         62 . The apparatus of  claim 57 , wherein the semiconductor chip includes a non-heat-generating region, and the arrangement includes the non-heat-generating region between a first circuit region of the plurality of circuit regions and a second circuit region of the plurality of circuit regions, the first circuit region and the second circuit region being accessed during the same time period. 
     
     
         63 . The apparatus of  claim 57 , wherein the difference in temperature within the semiconductor chip is further reduced as a result of a controlled access to each of the plurality of circuit regions. 
     
     
         64 . The apparatus of  claim 63 , wherein the semiconductor chip includes a dummy circuit region, and the controlled access includes accessing the dummy circuit region to decrease heat deformation of the semiconductor chip. 
     
     
         65 . A method comprising
 controlling access to each of a plurality of circuit regions of a semiconductor chip to reduce a difference in temperature within the semiconductor chip.   
     
     
         66 . The method of  claim 65 , wherein the controlling includes accessing non-adjacent circuit regions of the plurality of circuit regions at the same time. 
     
     
         67 . The method of  claim 65 , wherein the controlling includes controlling at least one of a frequency or a duration of access. 
     
     
         68 . The method of  claim 65 , wherein the controlling includes accessing a dummy circuit region included in the semiconductor chip. 
     
     
         69 . The method of  claim 65 , further comprising observing at least one of a frequency of access and a drive cycle of each of the plurality of circuit regions. 
     
     
         70 . The method of  claim 65 , further comprising estimating a difference of maximum and minimum temperatures of each circuit region. 
     
     
         71 . The method of  claim 70 , further comprising switching access from a first circuit region in the plurality of circuit regions to a second circuit region in the plurality of circuit regions when the difference is not within an allowable range, the first circuit region and the second circuit region having substantially similar functions.