On-chip capacitor structure

Abstract

At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

1 - 23 . (canceled) 
     
     
         24 . An apparatus comprising:
 a first metal-oxide-semiconductor (MOS) capacitor formed on a semiconductor substrate and connected to a first differential node;   a second MOS capacitor formed on the semiconductor substrate and connected to a second differential node; and   a first metal-insulator-metal (MIM) capacitor connected between the first differential node and the second differential node and formed at least partially above the first MOS capacitor.   
     
     
         25 . The apparatus of  claim 24 , wherein at least one layer of the first MOS capacitor comprises aluminum. 
     
     
         26 . The apparatus of  claim 24 , wherein at least one layer of the first MOS capacitor comprises copper. 
     
     
         27 . The apparatus of  claim 24 , wherein the first MOS capacitor comprises a first complementary metal-oxide semiconductor (CMOS) capacitor and the second MOS capacitor comprises a second CMOS capacitor. 
     
     
         28 . The apparatus of  claim 24 , wherein the first and second MOS capacitors are formed within a well of the semiconductor substrate. 
     
     
         29 . The apparatus of  claim 24 , wherein the first and second MOS capacitors are formed within an N-type well of the semiconductor substrate. 
     
     
         30 . The apparatus of  claim 24 , wherein the first MIM capacitor comprises an interdigitated capacitor. 
     
     
         31 . The apparatus of  claim 24 , wherein the first MIM capacitor is physically distinct from the first and second MOS capacitors. 
     
     
         32 . An apparatus comprising:
 a first metal-oxide-semiconductor (MOS) capacitive element formed on a semiconductor substrate and connected to a first differential node;   a second MOS capacitive element formed on the semiconductor substrate and connected to a second differential node; and   a first metal-insulator-metal (MIM) capacitive element connected between the first differential node and the second differential node and formed at least partially above the first MOS capacitive element.   
     
     
         33 . The apparatus of  claim 32 , wherein the first and second MOS capacitive elements have equal capacitances. 
     
     
         34 . The apparatus of  claim 32 , wherein the first and second MOS capacitive elements are formed within a well of the semiconductor substrate. 
     
     
         35 . The apparatus of  claim 32 , wherein the first MIM capacitive element comprises an interdigitated capacitor. 
     
     
         36 . The apparatus of  claim 32 , wherein the first MIM capacitive element is exclusive of the first and second MOS capacitive elements. 
     
     
         37 . A method comprising:
 forming, on a substrate, a first capacitor connected to a first differential node;   forming, on the substrate, a second capacitor connected to a second differential node; and   forming, on the substrate, a first interdigitated capacitor connected between the first differential node and the second differential node and formed at least partially above the first capacitor.   
     
     
         38 . The method of  claim 37 , wherein the substrate comprises a semiconductor substrate. 
     
     
         39 . The method of  claim 37 , wherein:
 the forming the first capacitor comprises forming the first capacitor within a well of the substrate; and   the forming the second capacitor comprises forming the second capacitor within the well of the substrate.   
     
     
         40 . The method of  claim 37 , further comprising forming, on the substrate, a second interdigitated capacitor connected between the first differential node and the second differential node and formed at least partially above the second capacitor. 
     
     
         41 . The method of  claim 37 , further comprising:
 coupling a switch with at least one of the first capacitor, the second capacitor, and the first interdigitated capacitor; and   coupling a control element with the switch, the control element being configured to cause a variation in an effective capacitance of at least one of the first capacitor, the second capacitor, and the first interdigitated capacitor by opening and closing the switch in response to temperature variation associated with the control element.   
     
     
         42 . An apparatus comprising:
 a first capacitor formed on a semiconductor substrate and connected to a first differential node;   a second capacitor formed on the semiconductor substrate and connected to a second differential node; and   a first interdigitated capacitor connected between the first differential node and the second differential node and formed at least partially above the first capacitor.   
     
     
         43 . The apparatus of  claim 42 , further comprising a second interdigitated capacitor connected between the first differential node and the second differential node and formed at least partially above the second capacitor.