Bipolar transistor manufacturing method

Abstract

A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

What is claimed is: 
     
         1 . A method for forming a bipolar transistor, the method comprising:
 forming a first doped region at a surface of a semiconductor substrate;   forming a semiconductor layer over the surface of the semiconductor substrate;   forming a first insulating layer between the first doped region and the semiconductor layer;   forming a stack that includes a silicon layer and a second insulating layer over the semiconductor layer;   forming an opening through said stack, said semiconductor layer, and the first insulating layer above the first doped region;   forming a single-crystal silicon region in said opening;   forming a silicon-germanium region at a surface of the single-crystal silicon region and in contact with side surfaces of the semiconductor layer and of the silicon layer; and   forming a second doped region in the opening and over the single-crystal silicon region.   
     
     
         2 . The method of  claim 1 , wherein the semiconductor layer has a thickness ranging approximately between 5 nm and 15 nm and the first insulating layer has a thickness ranging approximately between 10 nm and 50 nm. 
     
     
         3 . The method of  claim 1 , wherein prior to forming the first doped region, the method comprises forming shallow insulating trenches that extend into the semiconductor layer, the first insulating layer, and the semiconductor substrate. 
     
     
         4 . The method of  claim 1 , wherein forming the opening comprises etching a first opening having sidewalls through said stack and semiconductor layer, and etching a second opening through the first insulating layer, and before etching the second opening, the method comprises forming a third insulating layer on the walls of the first opening, and after forming a single-crystal silicon region in the opening, the method comprises removing the third insulating layer. 
     
     
         5 . The method of  claim 1 , wherein prior to forming a second doped region, the method comprises forming spacers on a portion of sidewalls of the opening. 
     
     
         6 . The method of  claim 1 , further comprising forming openings to access the first doped region and the silicon layer. 
     
     
         7 . The method of  claim 6 , wherein forming openings to access the silicon layer and the first doped region comprises in a first etch process, etching a portion of the second insulating layer, and in a second etch process, etching the silicon layer and of the semiconductor layer. 
     
     
         8 . The method of  claim 1 , further comprising annealing the substrate and layers. 
     
     
         9 . The method of  claim 1 , further comprising exposing the transistor to silicidation . 
     
     
         10 . The method of  claim 1 , wherein forming the second doped region in the opening and over the single-crystal silicon region comprises filling remaining portions of the opening with the second doped region. 
     
     
         11 . A bipolar transistor formed in a structure comprising:
 a semiconductor substrate having a first surface:   a semiconductor layer over the first surface of the semiconductor substrate with a first insulating layer located between the semiconductor substrate and the semiconductor layer;   a stack formed over the semiconductor layer, the stack including a silicon layer and a second insulating layer;   a collector region defined at the surface of the semiconductor substrate;   a base region that is in lateral contact with the semiconductor layer;   a buffer region located in an opening in the first insulating layer and between the base region and the collector region; and   an emitter region formed at the surface of said buffer region.   
     
     
         12 . The transistor of  claim 11 , wherein the semiconductor layer has a thickness ranging between approximately 5 nm and 15 nm and the insulating layer has a thickness ranging between approximately 10 nm and 50 nm. 
     
     
         13 . The transistor of  claim 11 , the base is made of a single-crystal silicon semiconductor material. 
     
     
         14 . The transistor of  claim 11 , wherein electrical connection to the base is provided through the at least one silicon layer by a vertical contact. 
     
     
         15 . An integrated circuit comprising:
 a MOS transistor; and   a bipolar transistor associated with the MOS transistor, the bipolar transistor including:
 a semiconductor substrate having a first surface: 
 a semiconductor layer located over the first surface of the semiconductor substrate with first insulating layer located between the semiconductor substrate and the semiconductor layer; 
 a stack formed over the semiconductor layer, the stack including a silicon layer and a second insulating layer; 
 a collector region located at the surface of the semiconductor substrate; 
 a base region that is formed from a single-crystal semiconductor material; and 
 a buffer region located in an opening in the first insulating layer and between the base region and the collector region. 
   
     
     
         16 . The integrated circuit of  claim 15 , further comprising an emitter region formed at the surface of said buffer region. 
     
     
         17 . The integrated circuit of  claim 15 , wherein electrical connection to the base is provided through the at least one silicon layer by a vertical contact therebetween. 
     
     
         18 . The integrated circuit of  claim 15 , further comprising contact pads that provide electrical contact to the collector and the base, respectively. 
     
     
         19 . The integrated circuit of  claim 15 , wherein the single-crystal semiconductor material is single-crystal silicon.