Impedance optimized chip system

Abstract

A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

1 - 9 . (canceled) 
     
     
         10 . A method for providing a multi-chip signal communication circuit within a given package, comprising:
 providing a given signal communication circuit;   assigning an initial segmentation of the signal communication circuit into an initial plurality of circuit segments;   generating an IC simulation model based on the plurality of circuit segments and a given characteristic impedance, the IC simulation model including an IC chip model for each of the circuit segments, and a modeled chip position and orientation for each of the IC chip models relative to modeled given chip package, each IC chip model including a plurality of modeled chip bond-wire pads, the IC simulation model including a plurality of modeled package bond-wire pads and a modeled bond wire connecting from at least one of the modeled package bond-wire pads to at least one of the modeled chip bond-wire pads, each modeled bond wire having a corresponding modeled length and modeled characteristic impedance, wherein the modeled chip positions and orientations provide each bond-wire model with a corresponding modeled length providing the modeled characteristic impedance; and   generating a fabrication data based on the IC simulation model.   
     
     
         11 . The method of  claim 10 , further comprising:
 generating an integrated circuit (IC) fabrication layout for each of the plurality of circuit segments, each of the IC fabrication layouts including a plurality of circuit input/output (I/O) points connected to a respective plurality of chip bond wire pads, each plurality of bond wire pads having a corresponding arrangement;   generating an IC simulation model for each of the IC fabrication layouts;   assigning, based on the IC simulation models, a location for each of the initial plurality of chips having an initial assignment of a plurality of high bandwidth bond wire pad;   calculating a characteristic impedance for a bond-wire connection from each of the plurality of the high-bandwidth bond-wire pads of the chip to a corresponding first terminal;   comparing the calculated characteristic impedance to a given characteristic impedance Z 0 ;   laterally displacing the at least one chip; and   repeating the calculating, comparing, and laterally displacing steps until either of the following conditions is detected:
 (i) the characteristic impedances are within a given tolerance from the given Z 0 ; or 
 (ii) the given tolerance cannot be met using the initial segmentation. 
   
     
     
         12 . The method of  claim 11 , wherein, if condition (ii) is detected, the method further comprises:
 updating the segmentation to generate an updated plurality of chips, at least one of the updated plurality of chips having an initial assignment of a plurality of high-bandwidth bond-wire pads; and   repeating the calculating, comparing, and laterally displacing the steps until either of the following conditions is detected:
 (i) the characteristic impedances are within a given tolerance from the given Z 0 ; or 
 (ii) the given tolerance cannot be met using the updated segmentation, and 
   updating, when condition (ii) is detected, the segmentation again; and   repeating the calculating, comparing, and laterally displacing steps until either of the following conditions is detected:
 (i) the characteristic impedances are within a given tolerance from the given Z 0 ; 
 (ii) the given tolerance cannot be met using the updated segmentation. 
   
     
     
         13 . A method for providing a multi-chip signal communication circuit within a given package having a chip support substrate, the package supporting first input/output terminals for carrying high-bandwidth signals at a given characteristic impedance Z 0 , and supporting a given plurality of second terminals for carrying low-bandwidth signals, the method comprising:
 assigning an initial segmentation defining an initial first chip and an initial second chip, at least one of the initial first chip having an initial assignment of at least one high bandwidth bond-wire pad;   defining an initial arrangement of bond-wire pads, the initial arrangement including an assignment of at least one high bandwidth bond wire pad to the first chip;   assigning an initial first location for the first chip on the substrate and an initial second location for the second chip on the substrate;   calculating a characteristic impedance for a bond-wire connection from each of a plurality of the high-bandwidth bond-wire pads to a corresponding first terminal;   comparing the calculated characteristic impedances to at least a given characteristic impedance Z 0 ; and   laterally displacing at least one of the first and second chips; and   repeating the calculating, comparing, and laterally displacing steps until either of the following conditions is detected:
 (i) the characteristic impedances are within a given tolerance from the given Z 0 ; or 
 (ii) the given tolerance cannot be met using the initial segmentation. 
   
     
     
         14 . The method of  claim 13 , wherein, if condition (ii) is detected, the method further comprises:
 updating the segmentation to generate an updated plurality of chips, at least one of the updated plurality of chips having an initial assignment of a plurality of high-bandwidth bond-wire pads; and   repeating the calculating, comparing, and laterally displacing the steps until either of the following conditions is detected:
 (i) the characteristic impedances are within a given tolerance from the given Z 0 ; or 
 (ii) the given tolerance cannot be met using the updated segmentation, and 
   updating, when condition (ii) is detected, the segmentation again; and   repeating the calculating, comparing, and laterally displacing steps until either of the following conditions is detected:
 (i) the characteristic impedances are within a given tolerance from the given Z 0 ; 
 (ii) the given tolerance cannot be met using the updated segmentation.