Self-aligned strap for embedded capacitor and replacement gate devices

Abstract

After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure comprising:
 forming a trench in a semiconductor substrate;   forming a node dielectric on a sidewall of said trench;   forming an inner electrode comprising a first doped semiconductor material within said node dielectric;   forming an access transistor on said semiconductor substrate, wherein said access transistor includes an access transistor source region comprising a second doped semiconductor material and contacting said node dielectric; and   forming a contacting said inner electrode, said node dielectric, and said access transistor source region.   
     
     
         2 . The method of  claim 1 , wherein said access transistor comprises an access transistor gate structure that includes a gate dielectric, a gate conductor contacting said gate dielectric, a dielectric gate cap contacting a top surface of said gate conductor, and a dielectric gate spacer contacting outer sidewalls of said gate dielectric. 
     
     
         3 . The method of  claim 2 , wherein said dielectric gate cap comprises a dielectric metal oxide having a dielectric constant greater than 8.0. 
     
     
         4 . The method of  claim 2 , further comprising:
 depositing a dielectric metal oxide layer having a dielectric constant greater than 8.0 on a top surface of gate conductors and a planar dielectric surface located at a same level as a topmost surface of said dielectric gate spacer; and   removing portions of said dielectric metal oxide layer from above said planar dielectric surface, wherein a remaining portion of said dielectric metal oxide layer constitutes said dielectric gate cap.   
     
     
         5 . The method of  claim 4 , further comprising:
 removing portions of a gate conductor layer from above said planar dielectric surface by planarization, wherein remaining portions of said gate conductor layer constitutes said gate conductors; and   recessing said gate conductors relative to said planar dielectric surface prior to deposition of said dielectric metal oxide layer.   
     
     
         6 . The method of  claim 5 , further comprising:
 recessing disposable gate structures below said planar dielectric surface to form gate cavities over said semiconductor substrate; and   forming a stack of a gate dielectric layer and said gate conductor layer in said gate cavities and on said planar dielectric surface.   
     
     
         7 . The method of  claim 2 , further comprising:
 forming a planarization dielectric layer on said semiconductor substrate after forming said gate dielectric and prior to forming said gate conductor and said gate dielectric cap;   forming a field effect transistor different from said access transistor on said semiconductor substrate, wherein said field effect transistor includes another dielectric gate spacer, a source region, and a drain region, wherein said source region and said drain region; and   removing said planarization dielectric layer from above said inner electrode and said access transistor source region, while said planarization dielectric layer is not removed from above said source region and said drain region.   
     
     
         8 . The method of  claim 7 , further comprising:
 forming a contact level dielectric layer on said metal semiconductor alloy portion and said source region and said drain region;   forming contact via cavities in said contact level dielectric layer, wherein portions of said source region and said drain region are exposed within said contact via cavities; and   forming additional metal semiconductor alloy portions on said source region and said drain region.   
     
     
         9 . The method of  claim 2 , further comprising:
 forming a planarization dielectric layer on said semiconductor substrate after forming said gate dielectric and prior to forming said gate conductor and said gate dielectric cap;   forming a field effect transistor different from said access transistor on said semiconductor substrate, wherein said field effect transistor includes another dielectric gate spacer, a source region, and a drain region, wherein said source region and said drain region; and   removing said planarization dielectric layer from above said inner electrode, said access transistor source region, said source region, and said drain region.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming additional metal semiconductor alloy portions on said source region and said drain region concurrently with formation of said metal semiconductor alloy portion; and   forming a contact level dielectric layer on said metal semiconductor alloy portion and said additional metal semiconductor alloy portions.   
     
     
         11 . The method of  claim 1 , further comprising forming a field effect transistor different from said access transistor on said semiconductor substrate, said field effect transistor including another dielectric gate spacer, a source region, and a drain region, wherein said source region and said drain region are laterally surrounded by a shallow trench isolation structure. 
     
     
         12 . The method of  claim 11 , further comprising forming at least another metal semiconductor alloy portion on said source region or said drain region and laterally spaced from at least one of said another dielectric gate spacer and said shallow trench isolation structure. 
     
     
         13 . The method of  claim 12 , further comprising:
 forming a planarization dielectric layer on sidewalls of said dielectric gate spacer and said another dielectric gate spacer; and   removing a portion of said planarization dielectric layer from above said access transistor source region prior to forming said metal semiconductor alloy portion.   
     
     
         14 . The method of  claim 13 , further comprising planarizing said planarization dielectric layer, wherein a top surface of said planarization dielectric layer is coplanar with a top surface of said gate dielectric of said access transistor after said planarizing. 
     
     
         15 . The method of  claim 13 , further comprising forming a contact level dielectric layer over said planarization dielectric layer. 
     
     
         16 . The method of  claim 15 , wherein said contact level dielectric layer is formed directly on said metal semiconductor alloy portion. 
     
     
         17 . The method of  claim 15 , further comprising forming a contact via cavity through said contact level dielectric layer and said planarization dielectric layer over said source region or drain region, wherein said at least another metal semiconductor alloy portion is formed at a bottom of said contact via cavity. 
     
     
         18 . The method of  claim 15 , wherein said contact level dielectric layer is deposited directly on a top surface of a gate dielectric of said access transistor. 
     
     
         19 . The method of  claim 15 , wherein a gate dielectric of said access transistor laterally surrounds a gate conductor of said access transistor, and said gate dielectric of said access transistor laterally surround a dielectric gate cap of said access transistor that overlies said gate conductor of said access transistor.