Embedded NOR Flash Memory Process with NAND Cell and True Logic Compatible Low Voltage Device

Abstract

An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

What is claimed is: 
     
         1 . A method for forming an integrated circuit on a substrate comprising the steps of:
 forming nonvolatile memory array circuits, logic circuits and linear analog circuits in active semiconductor areas;   separating the nonvolatile memory array circuits, the logic circuits and the linear analog circuits by isolation regions with a shallow trench isolation;   connecting the nonvolatile memory array circuits, the logic circuits and the linear analog circuits such that the nonvolatile memory array circuits, the logic circuits and the linear analog circuits are in intercommunication to transfer signals and data between them and external circuitry;   wherein forming the nonvolatile memory array circuits further comprises forming the nonvolatile memory circuits in a triple well structure by forming a first deep well with an impurity of a first conductivity type and forming a second well with an impurity of a second conductivity type in the first deep well; and   wherein forming the nonvolatile memory array circuits further comprises forming NAND-based NOR memory cells by forming at least two floating gate transistors, serially connecting the at least two floating gate transistors such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading.   
     
     
         2 . The method for forming the integrated circuit of  claim 1  wherein the impurity of the first conductivity type is an N-type impurity 
     
     
         3 . The method for forming the integrated circuit of  claim 1  wherein the impurity of the second conductivity type is a P-type impurity. 
     
     
         4 . The method for forming the integrated circuit of  claim 1  wherein forming the nonvolatile memory array circuits further comprises the step of: forming NAND and NAND-based NOR charge retaining cells in rows and columns of formed within designated active areas. 
     
     
         5 . The method for forming the integrated circuit of  claim 4  wherein forming NAND-based NOR charge retaining cells further comprises the steps of: associating each column of NAND-based NOR charge retaining cells with a bit line and a source line. 
     
     
         6 . The method for forming the integrated circuit of  claim 4  wherein forming NAND-based NOR charge retaining cells further comprises the steps of:
 connecting a drain of a topmost charge retaining transistor of each of the NAND-based NOR charge retaining cells to the bit line associated with and parallel to each of the columns of serially connected NAND-based NOR charge retaining cells; and 
 connecting a source of the bottommost charge retaining transistor of each of the NAND-based NOR charge retaining cells to a source line associated with and parallel to the column of NAND-based NOR charge retaining cells and parallel to the associated bit line. 
 
     
     
         7 . The method for forming the integrated circuit of  claim 4  wherein forming NAND-based NOR charge retaining cells comprises the step of: connecting a control gate of the NAND-based NOR flash memory cells of each of the rows to a word line. 
     
     
         8 . The method for forming the integrated circuit of  claim 1  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits in active semiconductor areas comprises the steps of:
 forming a shallow well of the first conductivity type and a shallow well of the second conductivity type; and 
 fabricating the low voltage logic and linear circuits in the first conductivity type and a shallow well of the second conductivity type. 
 
     
     
         9 . The method for forming the integrated circuit of  claim 8  wherein the shallow well of the first conductivity type is an N-well and the shallow well of the second conductivity type is a P-well. 
     
     
         10 . The method for forming the integrated circuit of  claim 9  wherein PMOS transistors are formed in the N-well and NMOS transistors are formed in the P-well. 
     
     
         11 . The method for forming the integrated circuit of  claim 1  further comprising the step of: forming high voltage MOS transistors in the substrate for the logic and linear analog circuits. 
     
     
         12 . The method for forming the integrated circuit of  claim 11  wherein forming high voltage MOS transistors comprises performing an ion implantation at the channel regions of the high voltage MOS transistors to establish the appropriate threshold. 
     
     
         13 . The method for forming the integrated circuit of  claim 12  wherein performing the ion implantation comprises the step of: performing a first ion implantation operation to set the threshold for the high voltage MOS transistor with a standard threshold voltage. 
     
     
         14 . The method for forming the integrated circuit of  claim 13  wherein performing the ion implantation further comprises the step of: performing a second ion implantation operation to set the threshold for a zero threshold high voltage MOS transistor. 
     
     
         15 . The method for forming the integrated circuit of  claim 1  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: applying a threshold setting implant to the channel regions of the charge retaining transistors of the NAND and NAND-based NOR memory arrays. 
     
     
         16 . The method for forming the integrated circuit of  claim 8  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: growing a high voltage thick insulation in active semiconductor areas for the logic circuits and linear analog circuits and the peripheral circuits for the nonvolatile memory circuits. 
     
     
         17 . The method for forming the integrated circuit of  claim 16  wherein the high voltage thick insulation layer is a nitride insulation layer grown on the surface of the substrate. 
     
     
         18 . The method for forming the integrated circuit of  claim 18  wherein forming nonvolatile memory array circuits further comprises the step of: forming a tunneling insulation layer is formed in the over the area of the charge retaining transistors of the nonvolatile memory circuits. 
     
     
         19 . The method for forming the integrated circuit of  claim 18  wherein the tunneling insulation layer is a tunneling oxide. 
     
     
         20 . The method for forming the integrated circuit of  claim 18  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: forming a first conductive layer on the substrate above the tunnel insulation layer and the thick insulation layer. 
     
     
         21 . The method for forming the integrated circuit of  claim 20  wherein the first conductive layer is a first polycrystalline silicon layer. 
     
     
         22 . The method for forming the integrated circuit of  claim 20  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: patterning the first conductive layer to define a floating gate for each of the floating gate charge retaining transistors. 
     
     
         23 . The method for forming the integrated circuit of  claim 22  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: forming a nitride layer and a second oxide layer on the tunneling oxide layer to form an oxide-nitride-oxide (ONO) charge retaining layer. 
     
     
         24 . The method for forming the integrated circuit of  claim 22  wherein separating the nonvolatile memory array circuits, the logic circuits and the linear analog circuits comprises the step of: defining an active area mask for the areas of the shallow trench isolation. 
     
     
         25 . The method for forming the integrated circuit of  claim 24  wherein separating the nonvolatile memory array circuits, the logic circuits and the linear analog circuits further comprises the step of: etching the defined areas of the active area mask create the trenches and filling the trenches with trench insulation. 
     
     
         26 . The method for forming the integrated circuit of  claim 25  wherein the trench insulation is a silicon oxide. 
     
     
         27 . The method for forming the integrated circuit of  claim 25  the shallow trench isolation self-aligns the charge retaining regions of the charge retaining transistors. 
     
     
         28 . The method for forming the integrated circuit of  claim 27  wherein the shallow trench isolation provides the self alignment of the first conductive layer to improve performance of the charge retaining transistors. 
     
     
         29 . The method for forming the integrated circuit of  claim 22  wherein separating the nonvolatile memory array circuits, the logic circuits and the linear analog circuits further comprises the step of: forming an inter-level dielectric on the first conductive layer. 
     
     
         30 . The method for forming the integrated circuit of  claim 28  wherein the inter-level dielectric layer is an oxide-nitride-oxide (ONO) formed by a high temperature chemical vapor deposition. 
     
     
         31 . The method for forming the integrated circuit of  claim 29  wherein separating the nonvolatile memory array circuits, the logic circuits and the linear analog circuits further comprises etching the inter-level dielectric in the active areas. 
     
     
         32 . The method for forming the integrated circuit of  claim 16  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: removing the high voltage thick insulation in the active areas for peripheral circuitry of the nonvolatile memory array circuits, the logic circuits, and the linear circuits having the low voltage transistors and growing a thin gate insulation in the regions defining low voltage transistors. 
     
     
         33 . The method for forming the integrated circuit of  claim 32  wherein the thin gate insulation is a silicon oxide. 
     
     
         34 . The method for forming the integrated circuit of  claim 29  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises forming a second conductive layer on the surface of the substrate. 
     
     
         35 . The method for forming the integrated circuit of  claim 34  wherein the second conductive layer is a second polycrystalline silicon that is deposited to thickness of from approximately 1,500 Å to 3,000 Å. 
     
     
         36 . The method for forming the integrated circuit of  claim 35  wherein the second polycrystalline silicon conductive layer is doped with an impurity to increase the conductivity of the second polycrystalline silicon conductive layer. 
     
     
         37 . The method for forming the integrated circuit of  claim 34  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the steps of:
 applying conductive films to a top surface of the second conductive layer to improve conductivity of the second conductive layer, and 
 depositing a capping layer over the second conductive layer to prevent peeling of conductive films 
 
     
     
         38 . The method for forming the integrated circuit of  claim 37  wherein the conductive films are tungsten. 
     
     
         39 . The method for forming the integrated circuit of  claim 34  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the steps of: applying a control gate mask to the second polycrystalline silicon conductive layer and the capping layer and defining the control gates of the charge retaining transistors and the gates of the NMOS and PMOS transistors of the peripheral circuits for the nonvolatile memory array circuits, logic circuits and linear analog circuits. 
     
     
         40 . The method for forming the integrated circuit of  claim 39  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits in active semiconductor areas further comprises the step of: forming a PMOS mask over the regions of the PMOS transistors to protect the regions of the PMOS transistors. 
     
     
         41 . The method for forming the integrated circuit of  claim 40  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits in active semiconductor areas further comprises the step of: implanting a first lightly doped drain (LDD) implant of an impurity of the first conductivity type to the surface of the substrate. 
     
     
         42 . The method for forming the integrated circuit of  claim 41  wherein the lightly doped drain implant is an arsenic implant or a phosphorus implant of a density of from approximately 1e12 to approximately 1e15. 
     
     
         43 . The method for forming the integrated circuit of  claim 41  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits in active semiconductor areas further comprises placing an NMOS mask over the regions of the NMOS transistors of the nonvolatile memory array, the peripheral circuits for the nonvolatile memory array circuits, logic circuits and linear analog circuits and implanting a second lightly doped drain implant of an impurity of the second conductivity type to the surface of the substrate. 
     
     
         44 . The method for forming the integrated circuit of  claim 43  wherein the lightly doped drain implant may be a boron implant or a boron di-flouride (BF2) implant of a density of from approximately 1e12 to approximately 1e15. 
     
     
         45 . The method for forming the integrated circuit of  claim 43  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: forming a peripheral implant mask over the substrate and leaving the nonvolatile memory array circuits exposed for a cell source and drain implant. 
     
     
         46 . The method for forming the integrated circuit of  claim 45  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: implanting a cell source/drain implant of the first conductivity type to form the source and drains for the charge retaining transistors wherein the stacked gate is self-aligning feature. 
     
     
         47 . The method for forming the integrated circuit of  claim 46  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: implanting a halo implant of the second conductivity type within the triple well against the junction walls to limit the extent of depletion regions prior to the cell source/drain implant. 
     
     
         48 . The method for forming the integrated circuit of  claim 46  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the steps of: forming a thick spacer insulation layer on the surface of the substrate and defining the thick spacer insulation layer to form spacers adjacent to the stacked gate structure of the charge retaining transistors and the gates of the NMOS and PMOS transistors. 
     
     
         49 . The method for forming the integrated circuit of  claim 48  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: applying a high voltage diffusion masking to the low voltage transistors and the nonvolatile memory array circuits. 
     
     
         50 . The method for forming the integrated circuit of  claim 49  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits in active semiconductor areas further comprises the step of: diffusing a double diffusion implant of the first conductivity type to the high voltage transistors to form the source and drain of the high voltage transistors. 
     
     
         51 . The method for forming the integrated circuit of  claim 50  wherein the double diffusion implant density is chosen such that the junction breakdown voltage is greater than approximately +20V. 
     
     
         52 . The method for forming the integrated circuit of  claim 49  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the steps of: removing the high voltage diffusion masking and applying a first low voltage diffusion masking to the regions of the nonvolatile memory array circuits, logic circuits and linear analog circuits having the second type conductivity and diffusing a first low voltage diffusion having a conductivity of the first type to the low voltage and high voltage transistors of the first conductivity type to form a shallow junction depth for low voltage applications and for a metal contact for the high voltage transistors. 
     
     
         53 . The method for forming the integrated circuit of  claim 49  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the steps of: covering the high voltage transistors with the first low voltage diffusion masking; removing the low voltage diffusion masking from the high voltage region; and creating a diffusion plug to make a contact region for the source and drains of the high voltage transistors. 
     
     
         54 . The method for forming the integrated circuit of  claim 52  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits in further comprises the steps of: removing the first low voltage diffusion masking is removed from the surface of the substrate and applying a second low voltage diffusion masking to the high and low voltage transistors of the first conductivity type. 
     
     
         55 . The method for forming the integrated circuit of  claim 54  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: implanting a second low voltage diffusion to the area of the transistors with the second conductivity type to create the source and drains of the transistors of the second conductivity type to form a shallow junction depth for low voltage applications. 
     
     
         56 . The method for forming the integrated circuit of  claim 55  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises forming a second interlayer dielectric on the surface of the substrate. 
     
     
         57 . The method for forming the integrated circuit of  claim 56  wherein the second interlayer dielectric is a borophosphosilicate glass (BPSG) or a phosphosilicate glass (PSG) formed by chemical vapor deposition followed by a chemical mechanical planarization. 
     
     
         58 . The method for forming the integrated circuit of  claim 56  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the steps of: forming and patterning a second interlayer photoresist layer on the second interlayer dielectric to expose the drain and source regions of the charge retaining transistors and the NMOS and PMOS transistors. 
     
     
         59 . The method for forming the integrated circuit of  claim 58  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: etching the second interlayer photoresist layer for exposing the drain and source regions of the charge retaining transistors and the NMOS and PMOS transistors. 
     
     
         60 . The method for forming the integrated circuit of  claim 59  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: forming contact regions to the sources and drains and filling the contact regions with a barrier metal. 
     
     
         61 . The method for forming the integrated circuit of  claim 60  wherein the barrier metal is Titanium Nitride/titanium alloy. 
     
     
         62 . The method for forming the integrated circuit of  claim 61  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: forming a first level metal on the surface of the second interlayer dielectric. 
     
     
         63 . The method for forming the integrated circuit of  claim 62  wherein forming the first level metal comprises the step of: sputtering the first level metal onto the surface of the substrate or electroplating the first level metal on the surface of the substrate. 
     
     
         64 . The method for forming the integrated circuit of  claim 62  wherein the first level metal is aluminum or is copper. 
     
     
         65 . The method for forming the integrated circuit of  claim 62  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: patterning the first level metal to form interconnections for the nonvolatile memory array circuits, logic circuits and linear analog circuits. 
     
     
         66 . The method for forming the integrated circuit of  claim 65  wherein forming nonvolatile memory array circuits, logic circuits and linear analog circuits further comprises the step of: forming additional layers of the interlayer dielectric and metal conductors to provide added interconnections for the nonvolatile memory array circuits, logic circuits and linear analog circuits.