US2013262734A1PendingUtilityA1

Modular scalable pci-express implementation

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Assignee: YAP KENG TECKPriority: Mar 31, 2008Filed: Sep 18, 2012Published: Oct 3, 2013
Est. expiryMar 31, 2028(~1.7 yrs left)· nominal 20-yr term from priority
Inventors:Keng Teck YapAzydee Hamid
G06F 13/36Y02D10/00G06F 13/4059G06F 2213/0026
37
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Claims

Abstract

In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 a functional PCI Express port including first buffers; and   an idle PCI Express port including second buffers;   wherein one or more of the second buffers are accessed by the functional PCI Express port.   
     
     
         2 . The apparatus of  claim 1 , wherein the one or more of the second buffers are used by the functional PCI Express port after all of the first buffers have been filled. 
     
     
         3 . The apparatus of  claim 1 , further comprising a common data bus coupled to the functional PCI Express port and coupled to the idle PCI Express port. 
     
     
         4 . The apparatus of  claim 1 , the functional PCI Express port including a controller to provide data between the functional PCI Express port and the second buffers. 
     
     
         5 . The apparatus of  claim 3 , the functional PCI Express port including a controller to provide data between the first buffers and the common data bus. 
     
     
         6 . The apparatus of  claim 1 , the idle PCI Express port including a controller to provide data between the second buffers and the functional PCI Express port. 
     
     
         7 . The apparatus of  claim 3 , the idle PCI Express port including a controller to provide input data between the second buffers and the functional PCI Express port via the common data bus. 
     
     
         8 . The apparatus of  claim 1 , further comprising a dock gating device to limit power provided to the idle PCI Express port. 
     
     
         9 . The apparatus of  claim 8 , wherein the clock gating device is to provide power to the second buffers. 
     
     
         10 . The apparatus of  claim 1 , further comprising one or more additional idle PCI Express port each including buffers, wherein one or more of the buffers included in at least one of the one or more additional idle PCI Express ports are accessed by the functional PCI Express port. 
     
     
         11 . The apparatus of  claim 10 , wherein one or more of the buffers of each of the one or more additional idle PCI Express ports are accessed by the functional PCI Express port. 
     
     
         12 . The apparatus of  claim 1 , wherein the apparatus is scalable such that any number of PCI Express ports may be included. 
     
     
         13 . The apparatus of  claim 12 , wherein each of the PCI Express ports may be a functional PCI Express port or an idle PCI Express port. 
     
     
         14 . The apparatus of  claim 1 , wherein each of PCI Express ports may be a functional PCI Express port or an idle PCI Express port. 
     
     
         15 . A method comprising:
 providing access to one or more buffers of a functional PCI Express pout; and   providing to the functional PCI Express port access to one or more buffers included in an idle PCI Express port.   
     
     
         16 . The method of  claim 15 , wherein the one or more of the buffers included in the idle PCI Express port are used by the functional PCI Express port after all of the buffers of the functional PCI Express port have been used. 
     
     
         17 . The method of  claim 15 , further comprising providing data between the functional PCI Express port and the buffers of the idle PCI Express port. 
     
     
         18 . The method of  claim 16 , further comprising limiting power provided to the idle PCI Express port. 
     
     
         19 . The method of  claim 18 , wherein the limiting includes providing power to the buffers of the idle PCI Express port. 
     
     
         20 . The method of  claim 15 , further comprising accessing by the functional PCI Express port one or more buffers included in each of one or more additional idle PCI Express ports. 
     
     
         21 . The method of  claim 20 , further comprising accessing by the functional PCI Express port one or more buffers included in all of a plurality of the one or more additional idle PCI Express ports. 
     
     
         22 . The method of  claim 15 , further comprising accessing by the functional PCI Express port one or more buffers included in all of a scalable number of additional idle PCI Express ports. 
     
     
         23 . The method of  claim 15 , wherein each of the PCI Express ports may be a functional PCI Express port or an idle PCI Express port. 
     
     
         24 . The method of  claim 23 , wherein each of the PCI Express ports may be a functional PCI Express port or an idle PCI Express port.

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