Processor for performing multiply-add operations on packed data

Abstract

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

What is claimed is: 
     
         1 . A processor comprising:
 a memory to store one or more instructions including a multiply-add instruction;   one or more execution units; and   a register file including a plurality of registers to store packed data, including a first 16-bit data element, a second 16-bit data element, a third 16-bit data element, and a fourth 16-bit data element in a first register and fifth 16-bit data element, a sixth 16-bit data element, a seventh 16-bit data element, and an eighth 16-bit data element in a second register;   wherein the one or more execution units are to generate a first 32-bit intermediate result equal to the first 16-bit data element multiplied by the fifth 16-bit data element, generate a second 32-bit intermediate result equal to the second 16-bit data element multiplied by the sixth 16-bit data element, generate a third 32-bit intermediate result equal to the third 16-bit data element multiplied by the seventh 16-bit data element, generate a fourth 32-bit intermediate result equal to the fourth 16-bit data element multiplied by the eighth 16-bit data element, and generate a first result data element equal to the first 32-bit intermediate result plus the second 32-bit intermediate result and a second result data element equal to the third 32-bit intermediate result plus the fourth 32-bit intermediate result.   
     
     
         2 . The processor of  claim 1  further including:
 storing said fifth intermediate result as a first data element of a third packed data and said sixth intermediate result as a second data element of said third packed data, wherein said third packed data includes only said first and second data elements, and 
 completing execution of said single instruction without adding said first and second data elements of said third packed data. 
 
     
     
         3 . The processor of  claim 1  further including:
 accessing said first, second, third, and fourth values from a storage area; and 
 writing said first packed data over said first, second, third, and fourth values in said storage area. 
 
     
     
         4 . The processor of  claim 1  further including:
 accessing said first, second, third, and fourth values from a register; and 
 writing said first packed data over said first, second, third, and fourth values in said register. 
 
     
     
         5 . A computer-implemented method comprising:
 responsive to the execution of a single instruction that specifies a first and second packed data including 16-bit data elements, wherein said 16-bit data elements of said first packed data comprise a first, second, third, and fourth value, and wherein said 16-bit data elements of said second packed data comprise a fifth, sixth, seventh, and eighth value, performing,   
       multiplying together said first value and fifth second value to generate a first 32-bit intermediate result;
 multiplying together said second value and said sixth value to generate a second 32-bit intermediate result; 
 multiplying together said third value and said seventh value to generate a third 32-bit intermediate result; 
 multiplying together said fourth value and said eighth value to generate a fourth 32-bit intermediate result; 
 adding together said first 32-bit intermediate result and said 32-bit second intermediate result to generate a first result data element; 
 adding together said third 32-bit intermediate result and said fourth 32-bit intermediate result to generate a second result data element. 
 
     
     
         6 . The method of  claim 5  further including:
 storing said fifth intermediate result as a first data element of a third packed data and said sixth intermediate result as a second data element of said third packed data, wherein said third packed data includes only said first and second data elements, and 
 completing execution of said single instruction without adding said first and second data elements of said third packed data. 
 
     
     
         7 . The method of  claim 6  further including:
 accessing said first, second, third, and fourth values from a storage area; and 
 writing said first packed data over said first, second, third, and fourth values in said storage area. 
 
     
     
         8 . The method of  claim 6  further including:
 accessing said first, second, third, and fourth values from a register; and 
 writing said first packed data over said first, second, third, and fourth values in said register.