US2013260554A1PendingUtilityA1

Semiconductor Devices and Methods of Manufacturing the Same

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Mar 4, 2010Filed: May 30, 2013Published: Oct 3, 2013
Est. expiryMar 4, 2030(~3.6 yrs left)· nominal 20-yr term from priority
H10D 64/011H10W 72/00H10W 20/032H10W 20/20H10D 30/69H10D 30/68H10D 64/666H10D 30/683H10D 30/60H10B 41/30H10B 41/40H10B 43/30H10B 43/40H01L 21/76841H01L 21/28
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Claims

Abstract

Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, comprising:
 forming a first conductive pattern including silicon doped with a first impurity of a first concentration on a lower structure; and   forming a second conductive pattern on the first conductive pattern, the second conductive pattern including metal silicide doped with a second impurity of a second concentration that is lower than the first concentration.   
     
     
         2 . The method of  claim 1 , wherein forming the second conductive pattern comprises:
 forming a second conductive layer including the silicon doped with the second impurity of the second concentration on the first conductive pattern; and   patterning the second conductive layer to form the second conductive pattern.   
     
     
         3 . The method of  claim 1 , wherein the first conductive layer comprises silicon doped with the first impurity including carbon (C), oxygen (O), nitrogen (N), germanium (Ge), arsenic (As), boron (B), fluorine (F) or combinations thereof, and
 wherein the second conductive layer comprises silicon doped with the second impurity including carbon (C), oxygen (O), nitrogen (N), germanium (Ge), arsenic (As), boron (B), fluorine (F) or combinations thereof.   
     
     
         4 . The method of  claim 1 , further comprising forming a third conductive pattern including silicon doped with a third impurity of a third concentration that is lower than the first concentration. 
     
     
         5 . The method of  claim 4 , wherein forming the third conductive pattern comprises:
 forming a third conductive layer comprising silicon doped with the second impurity including carbon (C), oxygen (O), nitrogen (N), germanium (Ge), arsenic (As), boron (B), fluorine (F) or combinations thereof; and   patterning the third conductive layer to form the third conductive pattern.   
     
     
         6 . The method of  claim 4 , wherein the first concentration is about ten times through about thirty times as high as the second and third concentrations. 
     
     
         7 . The method of  claim 4 , further comprising forming a fourth conductive pattern including silicon doped with a fourth impurity of a fourth concentration that is substantially lower than the first concentration, the fourth conductive pattern formed between the first conductive pattern and the second conductive pattern. 
     
     
         8 . The method of  claim 1 , wherein the lower structure comprises a charge storage pattern formed on a substrate and a dielectric pattern formed on the charge storage pattern.

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