Stacked semiconductor package and method for manufacturing the same

Abstract

A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

What is claimed is: 
     
         1 . A stacked semiconductor package comprising:
 a plurality of semiconductor package modules each including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, and formed adjoining one another in a matrix type such that through-holes of the semiconductor packages, which connect in a vertical direction, connect in a horizontal direction;   a main substrate supporting the semiconductor package modules and formed, on a third surface thereof facing the semiconductor package modules, with main connection pads which are aligned with the through-holes communicating in the vertical direction; and   conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.   
     
     
         2 . The stacked semiconductor package according to  claim 1 , wherein each of the semiconductor packages comprises:
 a substrate having a fifth surface, a sixth surface facing away from the fifth surface and sides surfaces connecting the fifth surface and the sixth surface, formed with connection pads on the fifth surface, and formed with the through-holes on the side surfaces;   a semiconductor chip placed on the substrate and having bonding pads which are connected with the connection pads; and   a mold part sealing the fifth surface of the substrate including the semiconductor chip and formed with the through-holes on side surfaces thereof.   
     
     
         3 . The stacked semiconductor package according to  claim 1 , wherein the substrate includes side pads which are formed on inner walls of the through-holes formed on the side surfaces of the substrate. 
     
     
         4 . The stacked semiconductor package according to  claim 1 , wherein the through-holes have the shape of a circular column or a prism with at least three sides. 
     
     
         5 . The stacked semiconductor package according to  claim 1 , wherein an open width of the through-holes, by which the through-holes are open on the side surfaces of the semiconductor package, has a size that is smaller than an inner diameter of the through-holes. 
     
     
         6 . The stacked semiconductor package according to  claim 5 , wherein the open width of the through-holes has a size that corresponds to approximately 10% to 50% of the inner diameter of the through-holes. 
     
     
         7 . The stacked semiconductor package according to  claim 1 , wherein the adhesive members are formed as flexible adhesive sheets. 
     
     
         8 . The stacked semiconductor package according to  claim 7 , wherein the adhesive members are formed using any one of a WBL (wafer backside lamination) film, a spacer tape, and a prepreg. 
     
     
         9 . The stacked semiconductor package according to  claim 1 , wherein the adhesive members are formed to partially cover cross-sections of the through-holes which are open on the first surface and the second surface of the semiconductor packages. 
     
     
         10 . The stacked semiconductor package according to  claim 9 , wherein the adhesive members are formed to cover approximately 20% to 50% of the cross-sections of the through-holes. 
     
     
         11 . The stacked semiconductor package according to  claim 1 , wherein the conductive connection members are formed using solder balls.