US2013250198A1PendingUtilityA1

Liquid crystal display device

Assignee: SHARP KKPriority: Mar 15, 2007Filed: May 9, 2013Published: Sep 26, 2013
Est. expiryMar 15, 2027(~0.6 yrs left)· nominal 20-yr term from priority
G09G 3/3648G09G 2300/0447G09G 3/3659G09G 2300/0876G09G 2300/0443G02F 1/134345G09G 2320/028G09G 2320/0233G02F 1/136213
57
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A liquid crystal display device according to the present invention includes: a plurality of pixels that are arranged in rows and columns so as to form a matrix pattern; and TFTs (TFT-A, TFT-B and TFT-C), source bus lines, gate bus lines and CS bus lines (CS-A and CS-B), which are associated with the respective pixels. Each pixel includes at least three subpixels (SP-A, SP-B and SP-C) with liquid crystal capacitors that are able to retain mutually different voltages. By supplying a signal (CS-A or CS-B) that makes two of the at least three subpixels display mutually different luminances at least at a certain grayscale tone from the source, gate and CS bus lines to each pixel, the at least three subpixels are able to display mutually different luminances.

Claims

exact text as granted — not AI-modified
1 - 3 . (canceled) 
     
     
         4 . A liquid crystal display device comprising: a plurality of pixels that are arranged in rows and columns so as to form a matrix pattern; and TFTs, source bus lines, gate bus lines and CS bus lines, which are associated with the respective pixels,
 wherein each said pixel includes at least three subpixels with liquid crystal capacitors that are able to retain mutually different voltages,   wherein by supplying a signal that makes two of the at least three subpixels display mutually different luminances at least at a certain grayscale tone from the source, gate and CS bus lines to each said pixel, the at least three subpixels are able to display mutually different luminances,   wherein each said pixel is associated with at least three TFTs for the at least three subpixels, one source bus line, at least one gate bus line and at least two CS bus lines,   wherein each of the TFTs associated with the at least three subpixels includes a gate electrode, a source electrode and a drain electrode,   wherein if the at least three subpixels are comprised of first, second and third subpixels and the at least two CS bus lines are comprised of first and second CS bus lines,   the first subpixel has a storage capacitor that is connected to the first CS bus line,   the second subpixel has a storage capacitor that is connected to the second CS bus line, and   the third subpixel has a storage capacitor that is connected to the first CS bus line and a storage capacitor that is connected to the second CS bus line.   
     
     
         5 . The liquid crystal display device of  claim 4 , wherein the gate bus line includes first and second gate lines, and
 wherein the first CS bus line includes first and second CS lines, and   wherein the second CS bus line includes third and fourth CS lines.   
     
     
         6 . The liquid crystal display device of  claim 5 , wherein the first and second gate lines, the first and second CS lines and the third and fourth CS lines are all branched within the liquid crystal display device. 
     
     
         7 . The liquid crystal display device of  claim 5 , wherein the first, second and third subpixels are arranged in a column direction, and
 wherein the third subpixel is arranged between the first and second subpixels.   
     
     
         8 . The liquid crystal display device of  claim 5 , wherein the third subpixel includes a TFT, of which the gate electrode is connected to the first gate line, and another TFT, of which the gate electrode is connected to the second gate line. 
     
     
         9 . The liquid crystal display device of  claim 5 , wherein the gate bus line further includes an interconnect that connects the first and second gate lines together, and
 wherein the CS bus line further includes an interconnect that connects the first and second CS lines together and/or an interconnect that connects the third and fourth CS lines together, and   wherein the interconnect of the gate bus line is made of the same material as the first and second gate lines of the gate bus line, and   wherein the interconnects of the CS bus line are made of the same material as the source bus line.   
     
     
         10 - 63 . (canceled)

Join the waitlist — get patent alerts

Track US2013250198A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.