Termination circuit for on-die termination

Abstract

In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

1 . A termination circuit for a terminal of a semiconductor device, the terminal associated with an expected voltage swing, the termination circuit comprising:
 a transistor connected between the terminal and a power supply at a supply voltage;   analog control circuitry for controllably enabling and disabling on-die termination, comprising calibrator circuitry with access to a reference resistance, the calibrator circuitry configured to carry out a calibration process for selecting one of a plurality of analog calibration voltages that would cause the transistor to impart a resistance substantially equal to a multiple of the reference resistance if supplied thereto as gate voltage,   wherein the control circuitry is configured to drive the gate of the transistor with said one of a plurality of analog calibration voltages when on-die termination is enabled, said one of a plurality of analog calibration voltages being outside a range of voltages defined by the supply voltage and the expected voltage swing.   
     
     
         2 . The termination circuit defined in  claim 1 , wherein the supply voltage is Vdd, 
     
     
         3 . The termination circuit defined in  claim 1 , wherein the supply voltage is substantially midway within the expected voltage swing. 
     
     
         4 . The termination circuit defined in  claim 3 , wherein the supply voltage is Vdd/2. 
     
     
         5 . The termination circuit defined in  claim 1 , wherein the termination circuit provides an electrical resistance between the power supply and the terminal, the electrical resistance being attributable in substantial part to the transistor. 
     
     
         6 . The termination circuit defined in  claim 1 , wherein the control circuitry is further configured to place the transistor in an off state when on-die termination is disabled. 
     
     
         7 . The termination circuit defined in  claim 6 , wherein the control circuitry comprises an input for receiving an enable signal indicative of whether on-die termination is enabled or disabled. 
     
     
         8 . The termination circuit defined in  claim 1 , wherein the reference resistor is an internal resistive device substantially matched to a resistance associated with resistive operation of the transistor. 
     
     
         9 . The termination circuit defined in  claim 1 , wherein the control circuitry further comprises a multiplexer for causing the analog calibration voltages to be delivered as the corresponding of transistor gate voltage, when on-die termination is enabled. 
     
     
         10 . The termination circuit defined in  claim 1 , wherein the calibrator circuitry comprises an internal circuit element exhibiting a behavior as a function of an applied voltage that corresponds to the behavior of the transistor as a function of the corresponding transistor gate voltage, wherein the calibration process comprises selecting the analog calibration voltage to be a voltage that results in the internal circuit element exhibiting a resistance that substantially matches the reference resistance. 
     
     
         11 . The termination circuit as defined in  claim 1 , wherein the multiple is a fraction. 
     
     
         12 . The termination circuit as defined in  claim 1 , wherein the multiple is equal to 1. 
     
     
         13 . The termination circuit as defined in  claim 1 , wherein the transistor is a PMOS transistor and said one of a plurality of analog calibration voltages being lower than the range of voltages defined by the supply voltage and the expected voltage swing. 
     
     
         14 . The termination circuit as defined in  claim 1 , wherein the transistor is a NMOS transistor and said one of a plurality of analog calibration voltages being higher than the range of voltages defined by the supply voltage and the expected voltage swing. 
     
     
         15 . A termination circuit for a terminal of a semiconductor device, the terminal associated with an expected voltage swing, the termination circuit comprising:
 A PMOS transistor connected between the terminal and a power supply at a supply voltage;   An NMOS transistor connected between the terminal and the power supply;   analog control circuitry for controllably enabling and disabling on-die termination, comprising calibrator circuitry with access to a reference resistance, the calibrator circuitry configured to carry out a calibration process for selecting one of a first plurality of analog calibration voltages that would cause the PMOS transistor to impart a resistance substantially equal to a first multiple of the reference resistance if supplied thereto as gate voltage, and to carry out a calibration process for selecting one of a second plurality of analog calibration voltages that would cause the NMOS transistor to impart a resistance substantially equal to a second multiple of the reference resistance if supplied thereto as gate voltage,   wherein the control circuitry is configured to drive the gate of the PMOS transistor with said one of a plurality of first analog calibration voltages and the gate of the NMOS transistor with said one of a second plurality of analog calibration voltages when on-die termination is enabled, said one of a plurality of first analog calibration voltages and said one of a plurality of second analog calibration voltages being outside a range of voltages defined by the supply voltage and the expected voltage swing.   
     
     
         16 . The termination circuit as defined in  claim 15 , wherein the first multiple and the second multiple are equal. 
     
     
         17 . The termination circuit as defined in  claim 16 , wherein the first multiple and the second multiple are fractions. 
     
     
         18 . The termination circuit as defined in  claim 15 , wherein the first multiple and the second multiple are equal to 1. 
     
     
         19 . A termination circuit for a terminal of a semiconductor device, the terminal associated with an expected voltage swing, the termination circuit comprising:
 A PMOS transistor connected between the terminal and a power supply at a high supply voltage;   An NMOS transistor connected between the terminal and a power supply at a low supply voltage;   analog control circuitry for controllably enabling and disabling on-die termination, comprising calibrator circuitry with access to a reference resistance, the calibrator circuitry configured to carry out a calibration process for selecting one of a first plurality of analog calibration voltages that would cause the PMOS transistor to impart a resistance substantially equal to a first multiple of the reference resistance if supplied thereto as gate voltage, and to carry out a calibration process for selecting one of a second plurality of analog calibration voltages that would cause the NMOS transistor to impart a resistance substantially equal to a second multiple of the reference resistance if supplied thereto as gate voltage,   wherein the control circuitry is configured to drive the gate of the PMOS transistor with said one of a plurality of first analog calibration voltages and the gate of the NMOS transistor with said one of a second plurality of analog calibration voltages when on-die termination is enabled, said one of a plurality of first analog calibration voltages and said one of a plurality of second analog calibration voltages being outside a range of voltages defined by the high supply voltage, the low supply voltage, and the expected voltage swing.   
     
     
         20 . The termination circuit as defined in  claim 19 , wherein the first multiple and the second multiple are equal. 
     
     
         21 . The termination circuit as defined in  claim 19 , wherein the high supply voltage is Vdd and the low supply voltage is Vss.