Same-Chip Multicharacteristic Semiconductor Structures

Abstract

In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor-on-insulator substrate comprised of a top semiconductor layer overlying an insulation layer, where the insulation layer overlies a bottom substrate layer;   at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion of the top semiconductor layer has a first thickness, a first width and a first depth; and   at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion of the top semiconductor layer has a second thickness, a second width and a second depth, where the first thickness and the second thickness are along a common first axis, where the first width and the second width are along a common second axis, where the first depth and the second depth are along a common third axis, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.   
     
     
         2 . The semiconductor structure of  claim 1 , where the at least one first device comprises at least one first transistor and the at least one second device comprises at least one second transistor, where the at least one first transistor comprises a first spacer having a first spacer thickness, where the at least one second transistor comprises a second spacer having a second spacer thickness, where the first spacer thickness is greater than the second spacer thickness. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising at least one raised source/drain structure coupled to at least one of the at least one first device and the at least one second device. 
     
     
         4 . The semiconductor structure of  1 , where the first portion is separated from the second portion by an isolation structure. 
     
     
         5 . The semiconductor structure of  claim 1 , where the semiconductor-on-insulator substrate comprises a thin semiconductor-on-insulator or an extremely thin silicon-on-insulator. 
     
     
         6 . The semiconductor structure of  claim 1 , where a difference between at least one of the first thickness and the second thickness, the first width and the second width, and the first depth and second depth is outside a range of normal tolerance. 
     
     
         7 . A semiconductor structure comprising:
 a substrate;   at least one first transistor at least partially overlying the substrate, where the at least one first transistor comprises a first spacer having a first spacer thickness; and   at least one second transistor at least partially overlying the substrate, where the at least one second transistor comprises a second spacer having a second spacer thickness, where the first spacer thickness is greater than the second spacer thickness.   
     
     
         8 . The semiconductor structure of  claim 7 , where the at least one first transistor comprises at least one first field effect transistor and the at least one second transistor comprises at least one second field effect transistor. 
     
     
         9 . The semiconductor structure of  claim 7 , further comprising at least one raised source/drain structure coupled to at least one of the at least one first transistor and the at least one second transistor. 
     
     
         10 . The semiconductor structure of  claim 7 , further comprising at least one first raised source/drain structure coupled to the at least one first transistor and at least one second raised source/drain structure coupled to the at least one second transistor, where the at least one first raised source/drain structure has a first length and the at least one second raised source/drain structure has a second length, where the first length is less than the second length. 
     
     
         11 . The semiconductor structure of  claim 7 , where the at least one first transistor is separated from the at least one second transistor by an isolation structure. 
     
     
         12 . The semiconductor structure of  claim 7 , where the substrate comprises a semiconductor-on-insulator substrate, a thin semiconductor-on-insulator substrate or an extremely thin semiconductor-on-insulator substrate. 
     
     
         13 . The semiconductor structure of  claim 7 , where a difference in thickness between the first spacer thickness and the second spacer thickness is outside a range of normal tolerance.